Searched refs:CLK_TOP_DDRPHYCFG_SEL (Results 1 – 19 of 19) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 94 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
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| H A D | mt7629-clk.h | 85 #define CLK_TOP_DDRPHYCFG_SEL 75 macro
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| H A D | mt8516-clk.h | 171 #define CLK_TOP_DDRPHYCFG_SEL 139 macro
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| H A D | mt7622-clk.h | 70 #define CLK_TOP_DDRPHYCFG_SEL 58 macro
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| H A D | mediatek,mt6795-clk.h | 92 #define CLK_TOP_DDRPHYCFG_SEL 81 macro
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| H A D | mt8173-clk.h | 94 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
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| H A D | mt2701-clk.h | 88 #define CLK_TOP_DDRPHYCFG_SEL 77 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 89 #define CLK_TOP_DDRPHYCFG_SEL 75 macro
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| H A D | mt7623-clk.h | 103 #define CLK_TOP_DDRPHYCFG_SEL 89 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 466 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
573 clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk); in mtk_topckgen_init()
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| H A D | clk-mt6795-topckgen.c | 456 TOP_MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
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| H A D | clk-mt8173-topckgen.c | 534 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
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| H A D | clk-mt8135.c | 383 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
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| H A D | clk-mt7622.c | 390 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
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| H A D | clk-mt8167.c | 559 MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
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| H A D | clk-mt2701.c | 491 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | mt7629.dtsi | 122 clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 366 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
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| H A D | clk-mt7623.c | 510 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
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