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Searched refs:BATL_PP_RW (Results 1 – 25 of 25) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dxpedite517x.h317 BATL_PP_RW |\
325 BATL_PP_RW |\
334 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
336 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
344 BATL_PP_RW |\
352 BATL_PP_RW |\
361 BATL_PP_RW |\
369 BATL_PP_RW |\
378 BATL_PP_RW |\
386 BATL_PP_RW |\
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H A DMPC8610HPCD.h286 #define CONFIG_SYS_DBAT0L (BATL_PP_RW)
287 #define CONFIG_SYS_IBAT0L (BATL_PP_RW)
296 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
299 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
307 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
310 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
318 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
321 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
326 | BATL_PP_RW | BATL_CACHEINHIBIT \
331 | BATL_PP_RW | BATL_CACHEINHIBIT)
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H A Dsbc8641d.h335 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
337 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
346 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
349 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
356 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
359 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
366 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
369 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
374 | BATL_PP_RW | BATL_CACHEINHIBIT \
379 | BATL_PP_RW | BATL_CACHEINHIBIT)
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H A DMPC8641HPCN.h422 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
423 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
430 | BATL_PP_RW | BATL_CACHEINHIBIT | \
436 | BATL_PP_RW | BATL_MEMCOHERENCE)
448 | BATL_PP_RW | BATL_CACHEINHIBIT \
454 | BATL_PP_RW | BATL_CACHEINHIBIT)
459 | BATL_PP_RW | BATL_CACHEINHIBIT | \
465 | BATL_PP_RW | BATL_CACHEINHIBIT)
474 | BATL_PP_RW | BATL_CACHEINHIBIT \
480 | BATL_PP_RW | BATL_CACHEINHIBIT)
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H A DTQM834x.h317 | BATL_PP_RW \
324 | BATL_PP_RW \
333 | BATL_PP_RW \
344 | BATL_PP_RW \
351 | BATL_PP_RW \
359 | BATL_PP_RW \
377 | BATL_PP_RW \
387 | BATL_PP_RW \
H A DMPC837XERDB.h505 | BATL_PP_RW \
515 | BATL_PP_RW \
526 | BATL_PP_RW \
538 | BATL_PP_RW \
550 | BATL_PP_RW \
557 | BATL_PP_RW \
563 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
574 | BATL_PP_RW \
584 | BATL_PP_RW \
H A DMPC837XEMDS.h490 | BATL_PP_RW \
500 | BATL_PP_RW \
511 | BATL_PP_RW \
523 | BATL_PP_RW \
535 | BATL_PP_RW \
542 | BATL_PP_RW \
548 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
559 | BATL_PP_RW \
569 | BATL_PP_RW \
H A DMPC832XEMDS.h423 | BATL_PP_RW \
434 | BATL_PP_RW \
446 | BATL_PP_RW \
458 | BATL_PP_RW \
465 | BATL_PP_RW \
476 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
487 | BATL_PP_RW \
497 | BATL_PP_RW \
H A Dvme8349.h400 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
408 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
412 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
424 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
428 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
440 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
445 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
450 BATL_PP_RW | BATL_MEMCOHERENCE)
H A DMPC8323ERDB.h341 | BATL_PP_RW \
352 | BATL_PP_RW \
364 | BATL_PP_RW \
371 | BATL_PP_RW \
382 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
393 | BATL_PP_RW \
403 | BATL_PP_RW \
H A DMPC8315ERDB.h456 | BATL_PP_RW \
467 | BATL_PP_RW \
479 | BATL_PP_RW \
486 | BATL_PP_RW \
492 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
502 | BATL_PP_RW \
513 | BATL_PP_RW \
H A Dsbc8349.h487 | BATL_PP_RW \
498 | BATL_PP_RW \
505 | BATL_PP_RW \
521 | BATL_PP_RW \
528 | BATL_PP_RW \
544 | BATL_PP_RW \
554 | BATL_PP_RW \
H A Dtuxx1.h158 BATL_PP_RW | \
166 BATL_PP_RW | \
178 BATL_PP_RW | \
185 BATL_PP_RW | \
H A Dsuvd3.h128 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
132 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
143 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
147 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
H A DMPC8349ITX.h537 | BATL_PP_RW \
547 | BATL_PP_RW \
554 | BATL_PP_RW \
570 | BATL_PP_RW \
577 | BATL_PP_RW \
593 | BATL_PP_RW \
603 | BATL_PP_RW \
H A Dve8313.h365 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
373 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
379 | BATL_PP_RW \
401 | BATL_PP_RW \
410 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
414 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
H A DMPC8349EMDS.h574 | BATL_PP_RW \
585 | BATL_PP_RW \
592 | BATL_PP_RW \
608 | BATL_PP_RW \
615 | BATL_PP_RW \
631 | BATL_PP_RW \
641 | BATL_PP_RW \
H A Dmpc8308_p1m.h402 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
410 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
418 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
422 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
428 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
H A DMPC8308RDB.h435 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
443 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
451 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
455 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
461 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
H A Dhrcon.h531 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
539 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
547 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
551 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
557 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
H A DMPC8313ERDB.h531 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
538 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
544 | BATL_PP_RW \
560 | BATL_PP_RW \
569 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
H A Dstrider.h563 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
571 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
579 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
583 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
589 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
/openbmc/u-boot/include/configs/km/
H A Dkm83xx-common.h224 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
232 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
240 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
244 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
249 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
253 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
258 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dmp.c111 bootpg | BATL_PP_RW | BATL_MEMCOHERENCE); in setup_mp()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dmmu.h176 #define BATL_PP_RW BATL_PP_10 macro