BATL_PP_RW (reference) in projects: openbmc

Searched refs:BATL_PP_RW (Results 1 – 25 of 25) sorted by relevance

/openbmc/u-boot/include/configs/
H A D	MPC8610HPCD.h	286 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 287 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 318 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR \| BATL_PP_RW \| BATL_CACHEINHIBIT \ 321 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR \| BATL_PP_RW \| BATL_CACHEINHIBIT) 326 \| BATL_PP_RW \| BATL_CACHEINHIBIT \ 331 \| BATL_PP_RW \| BATL_CACHEINHIBIT) 363 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| BATL_MEMCOHERENCE) 367 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY \| BATL_PP_RW \ 370 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY \| BATL_PP_RW \ 378 #define CONFIG_SYS_DBAT7L (PIXIS_BASE \| BATL_PP_RW \| BATL_CACHEINHIBIT \ [all …]
H A D	xpedite517x.h	`344 BATL_PP_RW \|\ 352 BATL_PP_RW \|\ 361 BATL_PP_RW \|\ 369 BATL_PP_RW \|\ 378 BATL_PP_RW \|\ 386 BATL_PP_RW \|\ 396 BATL_PP_RW \|\ 404 BATL_PP_RW \|\ 413 BATL_PP_RW \|\ 427 BATL_PP_RW \|\ [all …]`
H A D	sbc8641d.h	335 #define CONFIG_SYS_DBAT0L (BATL_PP_RW \| BATL_MEMCOHERENCE) 337 #define CONFIG_SYS_IBAT0L (BATL_PP_RW \| BATL_MEMCOHERENCE ) 346 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS \| BATL_PP_RW \ 356 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE \| BATL_PP_RW \ 366 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR \| BATL_PP_RW \ 374 \| BATL_PP_RW \| BATL_CACHEINHIBIT \ 379 \| BATL_PP_RW \| BATL_CACHEINHIBIT) 389 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS \| BATL_PP_RW \ 408 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) \| BATL_PP_RW \ 415 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY \| BATL_PP_RW \ [all …]
H A D	MPC8641HPCN.h	`430 \| BATL_PP_RW \| BATL_CACHEINHIBIT \| \ 436 \| BATL_PP_RW \| BATL_MEMCOHERENCE) 448 \| BATL_PP_RW \| BATL_CACHEINHIBIT \ 454 \| BATL_PP_RW \| BATL_CACHEINHIBIT) 465 \| BATL_PP_RW \| BATL_CACHEINHIBIT) 474 \| BATL_PP_RW \| BATL_CACHEINHIBIT \ 480 \| BATL_PP_RW \| BATL_CACHEINHIBIT) 499 \| BATL_PP_RW \| BATL_CACHEINHIBIT \ 505 \| BATL_PP_RW \| BATL_CACHEINHIBIT) 521 \| BATL_PP_RW \| BATL_CACHEINHIBIT \ [all …]`
H A D	TQM834x.h	`317 \| BATL_PP_RW \ 324 \| BATL_PP_RW \ 333 \| BATL_PP_RW \ 344 \| BATL_PP_RW \ 351 \| BATL_PP_RW \ 359 \| BATL_PP_RW \ 377 \| BATL_PP_RW \ 387 \| BATL_PP_RW \`
H A D	MPC837XERDB.h	`505 \| BATL_PP_RW \ 515 \| BATL_PP_RW \ 526 \| BATL_PP_RW \ 538 \| BATL_PP_RW \ 550 \| BATL_PP_RW \ 557 \| BATL_PP_RW \ 563 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW) 574 \| BATL_PP_RW \ 584 \| BATL_PP_RW \`
H A D	MPC837XEMDS.h	`490 \| BATL_PP_RW \ 500 \| BATL_PP_RW \ 511 \| BATL_PP_RW \ 523 \| BATL_PP_RW \ 535 \| BATL_PP_RW \ 542 \| BATL_PP_RW \ 548 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW) 559 \| BATL_PP_RW \ 569 \| BATL_PP_RW \`
H A D	MPC832XEMDS.h	`423 \| BATL_PP_RW \ 434 \| BATL_PP_RW \ 446 \| BATL_PP_RW \ 458 \| BATL_PP_RW \ 465 \| BATL_PP_RW \ 476 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW) 487 \| BATL_PP_RW \ 497 \| BATL_PP_RW \`
H A D	vme8349.h	400 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \ 408 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_RW \| \ 412 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \| BATL_PP_RW \| \ 424 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \| BATL_PP_RW \| \ 428 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \| BATL_PP_RW \| \ 440 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \ 445 #define CONFIG_SYS_IBAT6L (0xF0000000 \| BATL_PP_RW \| BATL_MEMCOHERENCE) 450 BATL_PP_RW \| BATL_MEMCOHERENCE)
H A D	MPC8323ERDB.h	`341 \| BATL_PP_RW \ 352 \| BATL_PP_RW \ 364 \| BATL_PP_RW \ 371 \| BATL_PP_RW \ 382 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW) 393 \| BATL_PP_RW \ 403 \| BATL_PP_RW \`
H A D	tuxx1.h	`158 BATL_PP_RW \| \ 166 BATL_PP_RW \| \ 178 BATL_PP_RW \| \ 185 BATL_PP_RW \| \`
H A D	suvd3.h	`128 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE \| BATL_PP_RW \| \ 132 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE \| BATL_PP_RW \| \ 143 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE \| BATL_PP_RW \| \ 147 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE \| BATL_PP_RW \| \`
H A D	sbc8349.h	`487 \| BATL_PP_RW \ 498 \| BATL_PP_RW \ 505 \| BATL_PP_RW \ 521 \| BATL_PP_RW \ 528 \| BATL_PP_RW \ 544 \| BATL_PP_RW \ 554 \| BATL_PP_RW \`
H A D	MPC8315ERDB.h	`456 \| BATL_PP_RW \ 467 \| BATL_PP_RW \ 479 \| BATL_PP_RW \ 486 \| BATL_PP_RW \ 492 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW) 502 \| BATL_PP_RW \ 513 \| BATL_PP_RW \`
H A D	ve8313.h	`365 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW) 373 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_RW) 379 \| BATL_PP_RW \ 401 \| BATL_PP_RW \ 410 #define CONFIG_SYS_IBAT6L (0xF0000000 \| BATL_PP_RW \| BATL_GUARDEDSTORAGE) 414 #define CONFIG_SYS_IBAT7L (0x60000000 \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)`
H A D	MPC8349ITX.h	`537 \| BATL_PP_RW \ 547 \| BATL_PP_RW \ 554 \| BATL_PP_RW \ 570 \| BATL_PP_RW \ 577 \| BATL_PP_RW \ 593 \| BATL_PP_RW \ 603 \| BATL_PP_RW \`
H A D	MPC8349EMDS.h	`574 \| BATL_PP_RW \ 585 \| BATL_PP_RW \ 592 \| BATL_PP_RW \ 608 \| BATL_PP_RW \ 615 \| BATL_PP_RW \ 631 \| BATL_PP_RW \ 641 \| BATL_PP_RW \`
H A D	mpc8308_p1m.h	`402 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \ 410 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \ 418 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 422 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 428 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)`
H A D	MPC8308RDB.h	`435 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \ 443 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \ 451 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 455 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 461 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)`
H A D	MPC8313ERDB.h	`531 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW) 538 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_RW) 544 \| BATL_PP_RW \ 560 \| BATL_PP_RW \ 569 #define CONFIG_SYS_IBAT6L (0xF0000000 \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)`
H A D	hrcon.h	`531 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \ 539 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \ 547 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 551 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 557 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)`
H A D	strider.h	`563 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \ 571 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \ 579 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 583 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 589 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)`
/openbmc/u-boot/include/configs/km/
H A D	km83xx-common.h	`224 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \ 232 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \ 240 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE \| BATL_PP_RW \| \ 244 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE \| BATL_PP_RW \| \ 249 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 253 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \ 258 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)`
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A D	mp.c	`111 bootpg \| BATL_PP_RW \| BATL_MEMCOHERENCE); in setup_mp()`
/openbmc/u-boot/arch/powerpc/include/asm/
H A D	mmu.h	`176 #define BATL_PP_RW BATL_PP_10 macro`

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