1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2264eaa0eSValentin Longchamp /* 3264eaa0eSValentin Longchamp * (C) Copyright 2010 4264eaa0eSValentin Longchamp * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5264eaa0eSValentin Longchamp */ 6264eaa0eSValentin Longchamp 7264eaa0eSValentin Longchamp #ifndef __CONFIG_KM83XX_H 8264eaa0eSValentin Longchamp #define __CONFIG_KM83XX_H 9264eaa0eSValentin Longchamp 10264eaa0eSValentin Longchamp /* include common defines/options for all Keymile boards */ 11264eaa0eSValentin Longchamp #include "keymile-common.h" 12264eaa0eSValentin Longchamp #include "km-powerpc.h" 13264eaa0eSValentin Longchamp 14264eaa0eSValentin Longchamp /* 15264eaa0eSValentin Longchamp * System Clock Setup 16264eaa0eSValentin Longchamp */ 17264eaa0eSValentin Longchamp #define CONFIG_83XX_CLKIN 66000000 18264eaa0eSValentin Longchamp #define CONFIG_SYS_CLK_FREQ 66000000 19264eaa0eSValentin Longchamp #define CONFIG_83XX_PCICLK 66000000 20264eaa0eSValentin Longchamp 21264eaa0eSValentin Longchamp /* 22264eaa0eSValentin Longchamp * IMMR new address 23264eaa0eSValentin Longchamp */ 24264eaa0eSValentin Longchamp #define CONFIG_SYS_IMMR 0xE0000000 25264eaa0eSValentin Longchamp 26264eaa0eSValentin Longchamp /* 27264eaa0eSValentin Longchamp * Bus Arbitration Configuration Register (ACR) 28264eaa0eSValentin Longchamp */ 29264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 30264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 31264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 32264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 33264eaa0eSValentin Longchamp 34264eaa0eSValentin Longchamp /* 35264eaa0eSValentin Longchamp * DDR Setup 36264eaa0eSValentin Longchamp */ 37264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 38264eaa0eSValentin Longchamp #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 390f2b721cSHolger Brunck #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ 400f2b721cSHolger Brunck 41264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 42264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 43264eaa0eSValentin Longchamp DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 44264eaa0eSValentin Longchamp 45264eaa0eSValentin Longchamp #define CFG_83XX_DDR_USES_CS0 46264eaa0eSValentin Longchamp 47264eaa0eSValentin Longchamp /* 48264eaa0eSValentin Longchamp * Manually set up DDR parameters 49264eaa0eSValentin Longchamp */ 50264eaa0eSValentin Longchamp #define CONFIG_DDR_II 51264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 52264eaa0eSValentin Longchamp 53264eaa0eSValentin Longchamp /* 54264eaa0eSValentin Longchamp * The reserved memory 55264eaa0eSValentin Longchamp */ 56264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 57264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BASE 0xF0000000 58264eaa0eSValentin Longchamp 59264eaa0eSValentin Longchamp #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 60264eaa0eSValentin Longchamp #define CONFIG_SYS_RAMBOOT 61264eaa0eSValentin Longchamp #endif 62264eaa0eSValentin Longchamp 63264eaa0eSValentin Longchamp /* Reserve 768 kB for Mon */ 64264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 65264eaa0eSValentin Longchamp 66264eaa0eSValentin Longchamp /* 67264eaa0eSValentin Longchamp * Initial RAM Base Address Setup 68264eaa0eSValentin Longchamp */ 69264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_LOCK 70264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 71264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 72264eaa0eSValentin Longchamp #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 73264eaa0eSValentin Longchamp GENERATED_GBL_DATA_SIZE) 74264eaa0eSValentin Longchamp 75264eaa0eSValentin Longchamp /* 76264eaa0eSValentin Longchamp * Init Local Bus Memory Controller: 77264eaa0eSValentin Longchamp * 78264eaa0eSValentin Longchamp * Bank Bus Machine PortSz Size Device 79264eaa0eSValentin Longchamp * ---- --- ------- ------ ----- ------ 80264eaa0eSValentin Longchamp * 0 Local GPCM 16 bit 256MB FLASH 81264eaa0eSValentin Longchamp * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 82264eaa0eSValentin Longchamp * 83264eaa0eSValentin Longchamp */ 84264eaa0eSValentin Longchamp /* 85264eaa0eSValentin Longchamp * FLASH on the Local Bus 86264eaa0eSValentin Longchamp */ 87264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 88264eaa0eSValentin Longchamp 89264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 907d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 91264eaa0eSValentin Longchamp 92264eaa0eSValentin Longchamp #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 937d6a0982SJoe Hershberger BR_PS_16 | /* 16 bit port size */ \ 947d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 95264eaa0eSValentin Longchamp BR_V) 96264eaa0eSValentin Longchamp 97264eaa0eSValentin Longchamp #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 98264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 99264eaa0eSValentin Longchamp OR_GPCM_SCY_5 | \ 1007d6a0982SJoe Hershberger OR_GPCM_TRLX_SET | OR_GPCM_EAD) 101264eaa0eSValentin Longchamp 102264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 103264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 104264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 105264eaa0eSValentin Longchamp 106264eaa0eSValentin Longchamp /* 107264eaa0eSValentin Longchamp * PRIO1/PIGGY on the local bus CS1 108264eaa0eSValentin Longchamp */ 109264eaa0eSValentin Longchamp /* Window base at flash base */ 110264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 1117d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 112264eaa0eSValentin Longchamp 113264eaa0eSValentin Longchamp #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 1147d6a0982SJoe Hershberger BR_PS_8 | /* 8 bit port size */ \ 1157d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 116264eaa0eSValentin Longchamp BR_V) 117264eaa0eSValentin Longchamp #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 118264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 119264eaa0eSValentin Longchamp OR_GPCM_SCY_2 | \ 1207d6a0982SJoe Hershberger OR_GPCM_TRLX_SET | OR_GPCM_EAD) 121264eaa0eSValentin Longchamp 122264eaa0eSValentin Longchamp /* 123264eaa0eSValentin Longchamp * Serial Port 124264eaa0eSValentin Longchamp */ 125264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_SERIAL 126264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_REG_SIZE 1 127264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 128264eaa0eSValentin Longchamp 129264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 130264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 131264eaa0eSValentin Longchamp 132264eaa0eSValentin Longchamp /* 133264eaa0eSValentin Longchamp * QE UEC ethernet configuration 134264eaa0eSValentin Longchamp */ 135264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH 136264eaa0eSValentin Longchamp #define CONFIG_ETHPRIME "UEC0" 137264eaa0eSValentin Longchamp 1385bcd64cfSKarlheinz Jerg #if !defined(CONFIG_MPC8309) 139264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH1 /* GETH1 */ 140264eaa0eSValentin Longchamp #define UEC_VERBOSE_DEBUG 1 1415bcd64cfSKarlheinz Jerg #endif 142264eaa0eSValentin Longchamp 143264eaa0eSValentin Longchamp #ifdef CONFIG_UEC_ETH1 144264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 145264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 146264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 147264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 148264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_PHY_ADDR 0 149264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 150264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 151264eaa0eSValentin Longchamp #endif 152264eaa0eSValentin Longchamp 153264eaa0eSValentin Longchamp /* 154264eaa0eSValentin Longchamp * Environment 155264eaa0eSValentin Longchamp */ 156264eaa0eSValentin Longchamp 157264eaa0eSValentin Longchamp #ifndef CONFIG_SYS_RAMBOOT 15868005ea6SValentin Longchamp #ifndef CONFIG_ENV_ADDR 159264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 160264eaa0eSValentin Longchamp CONFIG_SYS_MONITOR_LEN) 16168005ea6SValentin Longchamp #endif 162264eaa0eSValentin Longchamp #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 16368005ea6SValentin Longchamp #ifndef CONFIG_ENV_OFFSET 164264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 16568005ea6SValentin Longchamp #endif 166264eaa0eSValentin Longchamp 167264eaa0eSValentin Longchamp /* Address and size of Redundant Environment Sector */ 168264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 169264eaa0eSValentin Longchamp CONFIG_ENV_SECT_SIZE) 170264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 171264eaa0eSValentin Longchamp 172264eaa0eSValentin Longchamp #else /* CFG_SYS_RAMBOOT */ 173264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 174264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE 0x2000 175264eaa0eSValentin Longchamp #endif /* CFG_SYS_RAMBOOT */ 176264eaa0eSValentin Longchamp 177264eaa0eSValentin Longchamp /* I2C */ 17800f792e0SHeiko Schocher #define CONFIG_SYS_I2C 17900f792e0SHeiko Schocher #define CONFIG_SYS_NUM_I2C_BUSES 4 18000f792e0SHeiko Schocher #define CONFIG_SYS_I2C_MAX_HOPS 1 18100f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 18200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 200000 18300f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 18400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 185264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_OFFSET 0x3000 18600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 200000 18700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 18800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 18900f792e0SHeiko Schocher #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ 19000f792e0SHeiko Schocher {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 19100f792e0SHeiko Schocher {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 19200f792e0SHeiko Schocher {1, {I2C_NULL_HOP} } } 193264eaa0eSValentin Longchamp 194f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ 195264eaa0eSValentin Longchamp 196264eaa0eSValentin Longchamp #if defined(CONFIG_CMD_NAND) 197264eaa0eSValentin Longchamp #define CONFIG_NAND_KMETER1 198264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_NAND_DEVICE 1 199264eaa0eSValentin Longchamp #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 200264eaa0eSValentin Longchamp #endif 201264eaa0eSValentin Longchamp 202264eaa0eSValentin Longchamp /* 203264eaa0eSValentin Longchamp * For booting Linux, the board info and command line data 204264eaa0eSValentin Longchamp * have to be in the first 8 MB of memory, since this is 205264eaa0eSValentin Longchamp * the maximum mapped by the Linux kernel during initialization. 206264eaa0eSValentin Longchamp */ 207264eaa0eSValentin Longchamp #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 208264eaa0eSValentin Longchamp 209264eaa0eSValentin Longchamp /* 210264eaa0eSValentin Longchamp * Core HID Setup 211264eaa0eSValentin Longchamp */ 212264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_INIT 0x000000000 213264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 214264eaa0eSValentin Longchamp HID0_ENABLE_INSTRUCTION_CACHE) 215264eaa0eSValentin Longchamp #define CONFIG_SYS_HID2 HID2_HBE 216264eaa0eSValentin Longchamp 217264eaa0eSValentin Longchamp /* 218264eaa0eSValentin Longchamp * MMU Setup 219264eaa0eSValentin Longchamp */ 220264eaa0eSValentin Longchamp 221264eaa0eSValentin Longchamp #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 222264eaa0eSValentin Longchamp 223264eaa0eSValentin Longchamp /* DDR: cache cacheable */ 22472cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 225264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 226264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 227264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 228264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 229264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 230264eaa0eSValentin Longchamp 231264eaa0eSValentin Longchamp /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 23272cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 233264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 234264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 235264eaa0eSValentin Longchamp | BATU_VP) 236264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 237264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 238264eaa0eSValentin Longchamp 239264eaa0eSValentin Longchamp /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 24072cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 241264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 242264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 243264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 24472cd4087SJoe Hershberger #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 245264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 246264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 247264eaa0eSValentin Longchamp 248264eaa0eSValentin Longchamp /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 24972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 250264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 251264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 252264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 25372cd4087SJoe Hershberger #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 254264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 255264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 256264eaa0eSValentin Longchamp 257264eaa0eSValentin Longchamp /* Stack in dcache: cacheable, no memory coherence */ 25872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 259264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 260264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 261264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 262264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 263264eaa0eSValentin Longchamp 264264eaa0eSValentin Longchamp /* 265264eaa0eSValentin Longchamp * Internal Definitions 266264eaa0eSValentin Longchamp */ 267264eaa0eSValentin Longchamp #define BOOTFLASH_START 0xF0000000 268264eaa0eSValentin Longchamp 269264eaa0eSValentin Longchamp #define CONFIG_KM_CONSOLE_TTY "ttyS0" 270264eaa0eSValentin Longchamp 271264eaa0eSValentin Longchamp /* 272264eaa0eSValentin Longchamp * Environment Configuration 273264eaa0eSValentin Longchamp */ 274264eaa0eSValentin Longchamp #define CONFIG_ENV_OVERWRITE 275264eaa0eSValentin Longchamp #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 276264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV "km-common=empty\0" 277264eaa0eSValentin Longchamp #endif 278264eaa0eSValentin Longchamp 279b648bfc2SHolger Brunck #ifndef CONFIG_KM_DEF_ARCH 280b648bfc2SHolger Brunck #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 281264eaa0eSValentin Longchamp #endif 282264eaa0eSValentin Longchamp 283264eaa0eSValentin Longchamp #define CONFIG_EXTRA_ENV_SETTINGS \ 284264eaa0eSValentin Longchamp CONFIG_KM_DEF_ENV \ 285b648bfc2SHolger Brunck CONFIG_KM_DEF_ARCH \ 286264eaa0eSValentin Longchamp "newenv=" \ 28768005ea6SValentin Longchamp "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ 28868005ea6SValentin Longchamp "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ 289264eaa0eSValentin Longchamp "unlock=yes\0" \ 290264eaa0eSValentin Longchamp "" 291264eaa0eSValentin Longchamp 292264eaa0eSValentin Longchamp #if defined(CONFIG_UEC_ETH) 293264eaa0eSValentin Longchamp #define CONFIG_HAS_ETH0 294264eaa0eSValentin Longchamp #endif 295264eaa0eSValentin Longchamp 296264eaa0eSValentin Longchamp #endif /* __CONFIG_KM83XX_H */ 297