Lines Matching refs:BATL_PP_RW
335 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
337 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
346 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
349 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
356 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
359 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
366 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
369 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
374 | BATL_PP_RW | BATL_CACHEINHIBIT \
379 | BATL_PP_RW | BATL_CACHEINHIBIT)
389 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
392 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
399 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
408 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
411 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
415 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
418 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \