183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 296b8a054SScott Wood /* 3e8d3ca8bSScott Wood * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. 496b8a054SScott Wood */ 596b8a054SScott Wood /* 696b8a054SScott Wood * mpc8313epb board configuration file 796b8a054SScott Wood */ 896b8a054SScott Wood 996b8a054SScott Wood #ifndef __CONFIG_H 1096b8a054SScott Wood #define __CONFIG_H 1196b8a054SScott Wood 1296b8a054SScott Wood /* 1396b8a054SScott Wood * High Level Configuration Options 1496b8a054SScott Wood */ 1596b8a054SScott Wood #define CONFIG_E300 1 162c7920afSPeter Tyser #define CONFIG_MPC831x 1 1796b8a054SScott Wood #define CONFIG_MPC8313 1 1896b8a054SScott Wood #define CONFIG_MPC8313ERDB 1 1996b8a054SScott Wood 2022f4442dSScott Wood #ifdef CONFIG_NAND 2122f4442dSScott Wood #define CONFIG_SPL_INIT_MINIMAL 2222f4442dSScott Wood #define CONFIG_SPL_FLUSH_IMAGE 2322f4442dSScott Wood #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 2422f4442dSScott Wood #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND 2522f4442dSScott Wood 2622f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 2722f4442dSScott Wood #define CONFIG_NS16550_MIN_FUNCTIONS 2822f4442dSScott Wood #endif 2922f4442dSScott Wood 3022f4442dSScott Wood #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 3122f4442dSScott Wood #define CONFIG_SPL_MAX_SIZE (4 * 1024) 326113d3f2SBenoît Thébaudeau #define CONFIG_SPL_PAD_TO 0x4000 3322f4442dSScott Wood 34f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) 35f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 36f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 37f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 38f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 39f1c574d4SScott Wood #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) 40f1c574d4SScott Wood 4122f4442dSScott Wood #ifdef CONFIG_SPL_BUILD 42f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 4322f4442dSScott Wood #endif 4422f4442dSScott Wood 4522f4442dSScott Wood #endif /* CONFIG_NAND */ 46f1c574d4SScott Wood 47f1c574d4SScott Wood #ifndef CONFIG_SYS_MONITOR_BASE 48f1c574d4SScott Wood #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 49f1c574d4SScott Wood #endif 50f1c574d4SScott Wood 51842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 520914f483SBecky Bruce #define CONFIG_FSL_ELBC 1 5396b8a054SScott Wood 5489c7784eSTimur Tabi /* 5589c7784eSTimur Tabi * On-board devices 564ce1e23bSYork Sun * 574ce1e23bSYork Sun * TSEC1 is VSC switch 584ce1e23bSYork Sun * TSEC2 is SoC TSEC 5989c7784eSTimur Tabi */ 6089c7784eSTimur Tabi #define CONFIG_VSC7385_ENET 614ce1e23bSYork Sun #define CONFIG_TSEC2 6289c7784eSTimur Tabi 636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 645c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 665c5d3242SKim Phillips #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 6796b8a054SScott Wood #else 6896b8a054SScott Wood #error Unknown oscillator frequency. 6996b8a054SScott Wood #endif 7096b8a054SScott Wood 7196b8a054SScott Wood #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 7296b8a054SScott Wood 736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 7496b8a054SScott Wood 7522f4442dSScott Wood #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD) 766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR 77e4c09508SScott Wood #endif 78e4c09508SScott Wood 796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00001000 806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x07f00000 8196b8a054SScott Wood 8296b8a054SScott Wood /* Early revs of this board will lock up hard when attempting 8396b8a054SScott Wood * to access the PMC registers, unless a JTAG debugger is 8496b8a054SScott Wood * connected, or some resistor modifications are made. 8596b8a054SScott Wood */ 866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 8796b8a054SScott Wood 886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 9096b8a054SScott Wood 9196b8a054SScott Wood /* 9289c7784eSTimur Tabi * Device configurations 9389c7784eSTimur Tabi */ 9489c7784eSTimur Tabi 9589c7784eSTimur Tabi /* Vitesse 7385 */ 9689c7784eSTimur Tabi 9789c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 9889c7784eSTimur Tabi 994ce1e23bSYork Sun #define CONFIG_TSEC1 10089c7784eSTimur Tabi 10189c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 10289c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFE7FE000 10389c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 10489c7784eSTimur Tabi 10589c7784eSTimur Tabi #endif 10689c7784eSTimur Tabi 10789c7784eSTimur Tabi /* 10896b8a054SScott Wood * DDR Setup 10996b8a054SScott Wood */ 1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 11396b8a054SScott Wood 11496b8a054SScott Wood /* 11596b8a054SScott Wood * Manually set up DDR parameters, as this board does not 11696b8a054SScott Wood * seem to have the SPD connected to I2C. 11796b8a054SScott Wood */ 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1192e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1202fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1212fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 122261c07bcSJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 123261c07bcSJoe Hershberger | CSCONFIG_COL_BIT_10) 124e1d8ed2cSPoonam Aggrwal /* 0x80010102 */ 12596b8a054SScott Wood 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 12896b8a054SScott Wood | (0 << TIMING_CFG0_WRT_SHIFT) \ 12996b8a054SScott Wood | (0 << TIMING_CFG0_RRT_SHIFT) \ 13096b8a054SScott Wood | (0 << TIMING_CFG0_WWT_SHIFT) \ 13196b8a054SScott Wood | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 13296b8a054SScott Wood | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 13396b8a054SScott Wood | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 13496b8a054SScott Wood | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 13596b8a054SScott Wood /* 0x00220802 */ 1366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 137e1d8ed2cSPoonam Aggrwal | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 13896b8a054SScott Wood | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 13996b8a054SScott Wood | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 140e1d8ed2cSPoonam Aggrwal | (10 << TIMING_CFG1_REFREC_SHIFT) \ 14196b8a054SScott Wood | (3 << TIMING_CFG1_WRREC_SHIFT) \ 14296b8a054SScott Wood | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 14396b8a054SScott Wood | (2 << TIMING_CFG1_WRTORD_SHIFT)) 144e1d8ed2cSPoonam Aggrwal /* 0x3835a322 */ 1456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 146e1d8ed2cSPoonam Aggrwal | (5 << TIMING_CFG2_CPO_SHIFT) \ 14796b8a054SScott Wood | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 14896b8a054SScott Wood | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 14996b8a054SScott Wood | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 15096b8a054SScott Wood | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 151e1d8ed2cSPoonam Aggrwal | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 152e1d8ed2cSPoonam Aggrwal /* 0x129048c6 */ /* P9-45,may need tuning */ 1536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ 154e1d8ed2cSPoonam Aggrwal | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 155e1d8ed2cSPoonam Aggrwal /* 0x05100500 */ 15696b8a054SScott Wood #if defined(CONFIG_DDR_2T_TIMING) 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 158bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1592fef4020SJoe Hershberger | SDRAM_CFG_DBW_32 \ 1602fef4020SJoe Hershberger | SDRAM_CFG_2T_EN) 1612fef4020SJoe Hershberger /* 0x43088000 */ 16296b8a054SScott Wood #else 1636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 164bbea46f7SKim Phillips | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1652fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 16696b8a054SScott Wood /* 0x43080000 */ 16796b8a054SScott Wood #endif 1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_CFG2 0x00401000 16996b8a054SScott Wood /* set burst length to 8 for 32-bit data path */ 1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 171e1d8ed2cSPoonam Aggrwal | (0x0632 << SDRAM_MODE_SD_SHIFT)) 172e1d8ed2cSPoonam Aggrwal /* 0x44480632 */ 1736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x8000C000 17496b8a054SScott Wood 1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 17696b8a054SScott Wood /*0x02000000*/ 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 17896b8a054SScott Wood | DDRCDR_PZ_NOMZ \ 17996b8a054SScott Wood | DDRCDR_NZ_NOMZ \ 18096b8a054SScott Wood | DDRCDR_M_ODR) 18196b8a054SScott Wood 18296b8a054SScott Wood /* 18396b8a054SScott Wood * FLASH on the Local Bus 18496b8a054SScott Wood */ 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 18896b8a054SScott Wood 189261c07bcSJoe Hershberger #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 1907d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 1917d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 192261c07bcSJoe Hershberger | BR_V) /* valid */ 1937d6a0982SJoe Hershberger #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 19496b8a054SScott Wood | OR_GPCM_XACS \ 19596b8a054SScott Wood | OR_GPCM_SCY_9 \ 19696b8a054SScott Wood | OR_GPCM_EHTR \ 19796b8a054SScott Wood | OR_GPCM_EAD) 19896b8a054SScott Wood /* 0xFF006FF7 TODO SLOW 16 MB flash size */ 199261c07bcSJoe Hershberger /* window base at flash base */ 200261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2017d6a0982SJoe Hershberger /* 16 MB window size */ 2027d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 20396b8a054SScott Wood 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ 20696b8a054SScott Wood 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 20996b8a054SScott Wood 210261c07bcSJoe Hershberger #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ 21122f4442dSScott Wood !defined(CONFIG_SPL_BUILD) 2126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 21396b8a054SScott Wood #endif 21496b8a054SScott Wood 2156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 216261c07bcSJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 217553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 21896b8a054SScott Wood 219261c07bcSJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 220261c07bcSJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 22296b8a054SScott Wood 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 22416c8c170SKevin Hao #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 22696b8a054SScott Wood 22796b8a054SScott Wood /* 22896b8a054SScott Wood * Local Bus LCRR and LBCR regs 22996b8a054SScott Wood */ 230c7190f02SKim Phillips #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 231c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 2326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ 23396b8a054SScott Wood | (0xFF << LBCR_BMT_SHIFT) \ 23496b8a054SScott Wood | 0xF) /* 0x0004ff0f */ 23596b8a054SScott Wood 236261c07bcSJoe Hershberger /* LB refresh timer prescal, 266MHz/32 */ 237261c07bcSJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ 23896b8a054SScott Wood 239*a430fa06SMiquel Raynal /* drivers/mtd/nand/raw/nand.c */ 24022f4442dSScott Wood #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD) 2416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xFFF00000 242e4c09508SScott Wood #else 2436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0xE2800000 244e4c09508SScott Wood #endif 245e4c09508SScott Wood 246e8d3ca8bSScott Wood #define CONFIG_MTD_PARTITION 247e8d3ca8bSScott Wood 2486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 249acdab5c3SScott Wood #define CONFIG_NAND_FSL_ELBC 1 2506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 2517d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) 25296b8a054SScott Wood 2536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 2547d6a0982SJoe Hershberger | BR_DECC_CHK_GEN /* Use HW ECC */ \ 255261c07bcSJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 25696b8a054SScott Wood | BR_MS_FCM /* MSEL = FCM */ \ 25796b8a054SScott Wood | BR_V) /* valid */ 2587d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_OR_PRELIM \ 2597d6a0982SJoe Hershberger (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 26096b8a054SScott Wood | OR_FCM_CSCT \ 26196b8a054SScott Wood | OR_FCM_CST \ 26296b8a054SScott Wood | OR_FCM_CHT \ 26396b8a054SScott Wood | OR_FCM_SCY_1 \ 26496b8a054SScott Wood | OR_FCM_TRLX \ 26596b8a054SScott Wood | OR_FCM_EHTR) 26696b8a054SScott Wood /* 0xFFFF8396 */ 267e4c09508SScott Wood 26822f4442dSScott Wood #ifdef CONFIG_NAND 2696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM 2716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM 273e4c09508SScott Wood #else 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 2756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 2766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 2776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 278e4c09508SScott Wood #endif 279e4c09508SScott Wood 2806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 2817d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 28296b8a054SScott Wood 2836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 2846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 285e4c09508SScott Wood 2867d6a0982SJoe Hershberger /* local bus write LED / read status buffer (BCSR) mapping */ 2877d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_ADDR 0xFA000000 2887d6a0982SJoe Hershberger #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ 2897d6a0982SJoe Hershberger /* map at 0xFA000000 on LCS3 */ 2907d6a0982SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \ 2917d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 2927d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 2937d6a0982SJoe Hershberger | BR_V) /* valid */ 2947d6a0982SJoe Hershberger /* 0xFA000801 */ 2957d6a0982SJoe Hershberger #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ 2967d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 2977d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 2987d6a0982SJoe Hershberger | OR_GPCM_XACS \ 2997d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3007d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3017d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3027d6a0982SJoe Hershberger | OR_GPCM_EAD) 3037d6a0982SJoe Hershberger /* 0xFFFF8FF7 */ 3047d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR 3057d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 30696b8a054SScott Wood 30789c7784eSTimur Tabi /* Vitesse 7385 */ 30889c7784eSTimur Tabi 30989c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 31089c7784eSTimur Tabi 3117d6a0982SJoe Hershberger /* VSC7385 Base address on LCS2 */ 3127d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_BASE 0xF0000000 3137d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 3147d6a0982SJoe Hershberger 3157d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 3167d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit port */ \ 3177d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 3187d6a0982SJoe Hershberger | BR_V) /* valid */ 3197d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 3207d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 3217d6a0982SJoe Hershberger | OR_GPCM_XACS \ 3227d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 3237d6a0982SJoe Hershberger | OR_GPCM_SETA \ 3247d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 3257d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 3267d6a0982SJoe Hershberger | OR_GPCM_EAD) 3277d6a0982SJoe Hershberger /* 0xFFFE09FF */ 3287d6a0982SJoe Hershberger 329261c07bcSJoe Hershberger /* Access window base at VSC7385 base */ 330261c07bcSJoe Hershberger #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 3317d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 33289c7784eSTimur Tabi 33389c7784eSTimur Tabi #endif 33489c7784eSTimur Tabi 3350eaf8f9eSJoe Hershberger #define CONFIG_MPC83XX_GPIO 1 3360eaf8f9eSJoe Hershberger 33796b8a054SScott Wood /* 33896b8a054SScott Wood * Serial Port 33996b8a054SScott Wood */ 3406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 34296b8a054SScott Wood 3436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 34496b8a054SScott Wood {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 34596b8a054SScott Wood 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 34896b8a054SScott Wood 34996b8a054SScott Wood /* I2C */ 35000f792e0SHeiko Schocher #define CONFIG_SYS_I2C 35100f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 35200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 35300f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 35400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 35500f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 35600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 35700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 35800f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 35996b8a054SScott Wood 36096b8a054SScott Wood /* 36196b8a054SScott Wood * General PCI 36296b8a054SScott Wood * Addresses are mapped 1-1. 36396b8a054SScott Wood */ 3646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 3676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 37396b8a054SScott Wood 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 37596b8a054SScott Wood 37696b8a054SScott Wood /* 37789c7784eSTimur Tabi * TSEC 37896b8a054SScott Wood */ 37996b8a054SScott Wood 38089c7784eSTimur Tabi #define CONFIG_GMII /* MII PHY management */ 38189c7784eSTimur Tabi 38289c7784eSTimur Tabi #ifdef CONFIG_TSEC1 38389c7784eSTimur Tabi #define CONFIG_HAS_ETH0 38489c7784eSTimur Tabi #define CONFIG_TSEC1_NAME "TSEC0" 3856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 38689c7784eSTimur Tabi #define TSEC1_PHY_ADDR 0x1c 38789c7784eSTimur Tabi #define TSEC1_FLAGS TSEC_GIGABIT 38889c7784eSTimur Tabi #define TSEC1_PHYIDX 0 38996b8a054SScott Wood #endif 39096b8a054SScott Wood 39189c7784eSTimur Tabi #ifdef CONFIG_TSEC2 39289c7784eSTimur Tabi #define CONFIG_HAS_ETH1 393255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 39596b8a054SScott Wood #define TSEC2_PHY_ADDR 4 3963a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 39796b8a054SScott Wood #define TSEC2_PHYIDX 0 39889c7784eSTimur Tabi #endif 39989c7784eSTimur Tabi 40096b8a054SScott Wood /* Options are: TSEC[0-1] */ 40196b8a054SScott Wood #define CONFIG_ETHPRIME "TSEC1" 40296b8a054SScott Wood 40396b8a054SScott Wood /* 40496b8a054SScott Wood * Configure on-board RTC 40596b8a054SScott Wood */ 40696b8a054SScott Wood #define CONFIG_RTC_DS1337 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 40896b8a054SScott Wood 40996b8a054SScott Wood /* 41096b8a054SScott Wood * Environment 41196b8a054SScott Wood */ 41222f4442dSScott Wood #if defined(CONFIG_NAND) 4130e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET (512 * 1024) 4146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 4150e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 4160e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 4170e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) 418261c07bcSJoe Hershberger #define CONFIG_ENV_OFFSET_REDUND \ 419261c07bcSJoe Hershberger (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) 4206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif !defined(CONFIG_SYS_RAMBOOT) 421261c07bcSJoe Hershberger #define CONFIG_ENV_ADDR \ 422261c07bcSJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4230e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 4240e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 42596b8a054SScott Wood 42696b8a054SScott Wood /* Address and size of Redundant Environment Sector */ 42796b8a054SScott Wood #else 4286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4290e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 43096b8a054SScott Wood #endif 43196b8a054SScott Wood 43296b8a054SScott Wood #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 4336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 43496b8a054SScott Wood 4358ea5499aSJon Loeliger /* 436079a136cSJon Loeliger * BOOTP options 437079a136cSJon Loeliger */ 438079a136cSJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 439079a136cSJon Loeliger 440079a136cSJon Loeliger /* 4418ea5499aSJon Loeliger * Command line configuration. 4428ea5499aSJon Loeliger */ 4438ea5499aSJon Loeliger 44496b8a054SScott Wood /* 44596b8a054SScott Wood * Miscellaneous configurable options 44696b8a054SScott Wood */ 4476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 44996b8a054SScott Wood 450261c07bcSJoe Hershberger /* Boot Argument Buffer Size */ 451261c07bcSJoe Hershberger #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 45296b8a054SScott Wood 45396b8a054SScott Wood /* 45496b8a054SScott Wood * For booting Linux, the board info and command line data 4559f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 45696b8a054SScott Wood * the maximum mapped by the Linux kernel during initialization. 45796b8a054SScott Wood */ 458261c07bcSJoe Hershberger /* Initial Memory map for Linux*/ 459261c07bcSJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 46063865278SKevin Hao #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 46196b8a054SScott Wood 4626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 46396b8a054SScott Wood 4646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_66MHZ 46596b8a054SScott Wood 46696b8a054SScott Wood /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ 46796b8a054SScott Wood /* 0x62040000 */ 4686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 46996b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 47096b8a054SScott Wood HRCWL_DDRCM |\ 47196b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 47296b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 47396b8a054SScott Wood HRCWL_CSB_TO_CLKIN_2X1 |\ 47496b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 47596b8a054SScott Wood 4766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 477e4c09508SScott Wood 4786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_SYS_33MHZ) 47996b8a054SScott Wood 48096b8a054SScott Wood /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ 48196b8a054SScott Wood /* 0x65040000 */ 4826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 48396b8a054SScott Wood 0x20000000 /* reserved, must be set */ |\ 48496b8a054SScott Wood HRCWL_DDRCM |\ 48596b8a054SScott Wood HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 48696b8a054SScott Wood HRCWL_DDR_TO_SCB_CLK_2X1 |\ 48796b8a054SScott Wood HRCWL_CSB_TO_CLKIN_5X1 |\ 48896b8a054SScott Wood HRCWL_CORE_TO_CSB_2X1) 48996b8a054SScott Wood 4906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5) 491e4c09508SScott Wood 49296b8a054SScott Wood #endif 49396b8a054SScott Wood 4946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH_BASE (\ 49596b8a054SScott Wood HRCWH_PCI_HOST |\ 49696b8a054SScott Wood HRCWH_PCI1_ARBITER_ENABLE |\ 49796b8a054SScott Wood HRCWH_CORE_ENABLE |\ 49896b8a054SScott Wood HRCWH_BOOTSEQ_DISABLE |\ 49996b8a054SScott Wood HRCWH_SW_WATCHDOG_DISABLE |\ 50096b8a054SScott Wood HRCWH_TSEC1M_IN_RGMII |\ 50196b8a054SScott Wood HRCWH_TSEC2M_IN_RGMII |\ 502e4c09508SScott Wood HRCWH_BIG_ENDIAN) 503e4c09508SScott Wood 50422f4442dSScott Wood #ifdef CONFIG_NAND 5056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 506e4c09508SScott Wood HRCWH_FROM_0XFFF00100 |\ 507e4c09508SScott Wood HRCWH_ROM_LOC_NAND_SP_8BIT |\ 508e4c09508SScott Wood HRCWH_RL_EXT_NAND) 509e4c09508SScott Wood #else 5106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ 511e4c09508SScott Wood HRCWH_FROM_0X00000100 |\ 512e4c09508SScott Wood HRCWH_ROM_LOC_LOCAL_16BIT |\ 513e4c09508SScott Wood HRCWH_RL_EXT_LEGACY) 514e4c09508SScott Wood #endif 51596b8a054SScott Wood 51696b8a054SScott Wood /* System IO Config */ 5176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ 5180eaf8f9eSJoe Hershberger /* Enable Internal USB Phy and GPIO on LCD Connector */ 5190eaf8f9eSJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) 52096b8a054SScott Wood 5216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_INIT 0x000000000 5226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 5231a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE | \ 52496b8a054SScott Wood HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 52596b8a054SScott Wood 5266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 52796b8a054SScott Wood 52831d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 52931d82672SBecky Bruce 53096b8a054SScott Wood /* DDR @ 0x00000000 */ 53172cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 532261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 533261c07bcSJoe Hershberger | BATU_BL_256M \ 534261c07bcSJoe Hershberger | BATU_VS \ 535261c07bcSJoe Hershberger | BATU_VP) 53696b8a054SScott Wood 53796b8a054SScott Wood /* PCI @ 0x80000000 */ 53872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 539261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 540261c07bcSJoe Hershberger | BATU_BL_256M \ 541261c07bcSJoe Hershberger | BATU_VS \ 542261c07bcSJoe Hershberger | BATU_VP) 543261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 54472cd4087SJoe Hershberger | BATL_PP_RW \ 545261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 546261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 547261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 548261c07bcSJoe Hershberger | BATU_BL_256M \ 549261c07bcSJoe Hershberger | BATU_VS \ 550261c07bcSJoe Hershberger | BATU_VP) 55196b8a054SScott Wood 55296b8a054SScott Wood /* PCI2 not supported on 8313 */ 5536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L (0) 5546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U (0) 5556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L (0) 5566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U (0) 55796b8a054SScott Wood 55896b8a054SScott Wood /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 559261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 56072cd4087SJoe Hershberger | BATL_PP_RW \ 561261c07bcSJoe Hershberger | BATL_CACHEINHIBIT \ 562261c07bcSJoe Hershberger | BATL_GUARDEDSTORAGE) 563261c07bcSJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 564261c07bcSJoe Hershberger | BATU_BL_256M \ 565261c07bcSJoe Hershberger | BATU_VS \ 566261c07bcSJoe Hershberger | BATU_VP) 56796b8a054SScott Wood 56896b8a054SScott Wood /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 56972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 5706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 57196b8a054SScott Wood 5726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L (0) 5736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U (0) 57496b8a054SScott Wood 5756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 5776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 5786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 5796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 5806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 5816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 5826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 5836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 5846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 5896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 5906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 59196b8a054SScott Wood 59296b8a054SScott Wood /* 59396b8a054SScott Wood * Environment Configuration 59496b8a054SScott Wood */ 59596b8a054SScott Wood #define CONFIG_ENV_OVERWRITE 59696b8a054SScott Wood 597261c07bcSJoe Hershberger #define CONFIG_NETDEV "eth1" 59896b8a054SScott Wood 5995bc0543dSMario Six #define CONFIG_HOSTNAME "mpc8313erdb" 6008b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfs/root/path" 601b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 602261c07bcSJoe Hershberger /* U-Boot image on TFTP server */ 603261c07bcSJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 604261c07bcSJoe Hershberger #define CONFIG_FDTFILE "mpc8313erdb.dtb" 60596b8a054SScott Wood 606261c07bcSJoe Hershberger /* default location for tftp and bootm */ 607261c07bcSJoe Hershberger #define CONFIG_LOADADDR 800000 60896b8a054SScott Wood 60996b8a054SScott Wood #define CONFIG_EXTRA_ENV_SETTINGS \ 610261c07bcSJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 61196b8a054SScott Wood "ethprime=TSEC1\0" \ 612261c07bcSJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 61396b8a054SScott Wood "tftpflash=tftpboot $loadaddr $uboot; " \ 6145368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 6155368c55dSMarek Vasut " +$filesize; " \ 6165368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 6175368c55dSMarek Vasut " +$filesize; " \ 6185368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6195368c55dSMarek Vasut " $filesize; " \ 6205368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 6215368c55dSMarek Vasut " +$filesize; " \ 6225368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6235368c55dSMarek Vasut " $filesize\0" \ 62479f516bcSKim Phillips "fdtaddr=780000\0" \ 625261c07bcSJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" \ 62696b8a054SScott Wood "console=ttyS0\0" \ 62796b8a054SScott Wood "setbootargs=setenv bootargs " \ 62896b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 62996b8a054SScott Wood "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 630261c07bcSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 631261c07bcSJoe Hershberger "$netdev:off " \ 63296b8a054SScott Wood "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 63396b8a054SScott Wood 63496b8a054SScott Wood #define CONFIG_NFSBOOTCOMMAND \ 63596b8a054SScott Wood "setenv rootdev /dev/nfs;" \ 63696b8a054SScott Wood "run setbootargs;" \ 63796b8a054SScott Wood "run setipargs;" \ 63896b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 63996b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 64096b8a054SScott Wood "bootm $loadaddr - $fdtaddr" 64196b8a054SScott Wood 64296b8a054SScott Wood #define CONFIG_RAMBOOTCOMMAND \ 64396b8a054SScott Wood "setenv rootdev /dev/ram;" \ 64496b8a054SScott Wood "run setbootargs;" \ 64596b8a054SScott Wood "tftp $ramdiskaddr $ramdiskfile;" \ 64696b8a054SScott Wood "tftp $loadaddr $bootfile;" \ 64796b8a054SScott Wood "tftp $fdtaddr $fdtfile;" \ 64896b8a054SScott Wood "bootm $loadaddr $ramdiskaddr $fdtaddr" 64996b8a054SScott Wood 65096b8a054SScott Wood #endif /* __CONFIG_H */ 651