1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22ad6b513STimur Tabi /* 34c2e3da8SKumar Gala * Copyright (C) Freescale Semiconductor, Inc. 2006. 42ad6b513STimur Tabi */ 52ad6b513STimur Tabi 62ad6b513STimur Tabi /* 77a78f148STimur Tabi MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 82ad6b513STimur Tabi 92ad6b513STimur Tabi Memory map: 102ad6b513STimur Tabi 112ad6b513STimur Tabi 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 122ad6b513STimur Tabi 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 132ad6b513STimur Tabi 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 142ad6b513STimur Tabi 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 152ad6b513STimur Tabi 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 162ad6b513STimur Tabi 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 177a78f148STimur Tabi 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 182ad6b513STimur Tabi 0xF001_0000-0xF001_FFFF Local bus expansion slot 197a78f148STimur Tabi 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 207a78f148STimur Tabi 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 217a78f148STimur Tabi 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 222ad6b513STimur Tabi 232ad6b513STimur Tabi I2C address list: 242ad6b513STimur Tabi Align. Board 252ad6b513STimur Tabi Bus Addr Part No. Description Length Location 262ad6b513STimur Tabi ---------------------------------------------------------------- 27be5e6181STimur Tabi I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 282ad6b513STimur Tabi 29be5e6181STimur Tabi I2C1 0x20 PCF8574 I2C Expander 0 U8 30be5e6181STimur Tabi I2C1 0x21 PCF8574 I2C Expander 0 U10 31be5e6181STimur Tabi I2C1 0x38 PCF8574A I2C Expander 0 U8 32be5e6181STimur Tabi I2C1 0x39 PCF8574A I2C Expander 0 U10 33be5e6181STimur Tabi I2C1 0x51 (DDR) DDR EEPROM 1 U1 34be5e6181STimur Tabi I2C1 0x68 DS1339 RTC 1 U68 352ad6b513STimur Tabi 362ad6b513STimur Tabi Note that a given board has *either* a pair of 8574s or a pair of 8574As. 372ad6b513STimur Tabi */ 382ad6b513STimur Tabi 392ad6b513STimur Tabi #ifndef __CONFIG_H 402ad6b513STimur Tabi #define __CONFIG_H 412ad6b513STimur Tabi 4214d0a02aSWolfgang Denk #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOWBOOT 447a78f148STimur Tabi #endif 452ad6b513STimur Tabi 462ad6b513STimur Tabi /* 472ad6b513STimur Tabi * High Level Configuration Options 482ad6b513STimur Tabi */ 492c7920afSPeter Tyser #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 502ad6b513STimur Tabi #define CONFIG_MPC8349 /* MPC8349 specific */ 512ad6b513STimur Tabi 526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 532ad6b513STimur Tabi 5489c7784eSTimur Tabi #define CONFIG_MISC_INIT_F 557a78f148STimur Tabi 5689c7784eSTimur Tabi /* 5789c7784eSTimur Tabi * On-board devices 5889c7784eSTimur Tabi */ 597a78f148STimur Tabi 607a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 61396abba2SJoe Hershberger /* The CF card interface on the back of the board */ 62396abba2SJoe Hershberger #define CONFIG_COMPACT_FLASH 6389c7784eSTimur Tabi #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 64c31e1326SValeriy Glushkov #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 657a78f148STimur Tabi #endif 667a78f148STimur Tabi 672ad6b513STimur Tabi #define CONFIG_RTC_DS1337 6800f792e0SHeiko Schocher #define CONFIG_SYS_I2C 697a78f148STimur Tabi 707a78f148STimur Tabi /* 717a78f148STimur Tabi * Device configurations 727a78f148STimur Tabi */ 732ad6b513STimur Tabi 742ad6b513STimur Tabi /* I2C */ 7500f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 7600f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 7700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 7800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 7900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 8000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 8100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 8200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 832ad6b513STimur Tabi 846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 85b7be63abSValeriy Glushkov #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 862ad6b513STimur Tabi 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 93be5e6181STimur Tabi #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 942ad6b513STimur Tabi 952ad6b513STimur Tabi /* Don't probe these addresses: */ 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD {1, CONFIG_SYS_I2C_8574A_ADDR2} } 1002ad6b513STimur Tabi /* Bit definitions for the 8574[A] I2C expander */ 101396abba2SJoe Hershberger /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 102396abba2SJoe Hershberger #define I2C_8574_REVISION 0x03 1032ad6b513STimur Tabi #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 1042ad6b513STimur Tabi #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 1052ad6b513STimur Tabi #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 1062ad6b513STimur Tabi #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 1072ad6b513STimur Tabi 1082ad6b513STimur Tabi #endif 1092ad6b513STimur Tabi 1107a78f148STimur Tabi /* Compact Flash */ 1112ad6b513STimur Tabi #ifdef CONFIG_COMPACT_FLASH 1122ad6b513STimur Tabi 1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXBUS 1 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IDE_MAXDEVICE 1 1152ad6b513STimur Tabi 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_REG_OFFSET 0 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ATA_STRIDE 2 1222ad6b513STimur Tabi 123396abba2SJoe Hershberger /* If a CF card is not inserted, time out quickly */ 124396abba2SJoe Hershberger #define ATA_RESET_TIME 1 1252ad6b513STimur Tabi 126c9e34fe2SValeriy Glushkov #endif 127c9e34fe2SValeriy Glushkov 128c9e34fe2SValeriy Glushkov /* 129c9e34fe2SValeriy Glushkov * SATA 130c9e34fe2SValeriy Glushkov */ 131c9e34fe2SValeriy Glushkov #ifdef CONFIG_SATA_SIL3114 132c9e34fe2SValeriy Glushkov 133c9e34fe2SValeriy Glushkov #define CONFIG_SYS_SATA_MAX_DEVICE 4 134c9e34fe2SValeriy Glushkov #define CONFIG_LBA48 1352ad6b513STimur Tabi 1367a78f148STimur Tabi #endif 1372ad6b513STimur Tabi 138c31e1326SValeriy Glushkov #ifdef CONFIG_SYS_USB_HOST 139c31e1326SValeriy Glushkov /* 140c31e1326SValeriy Glushkov * Support USB 141c31e1326SValeriy Glushkov */ 142c31e1326SValeriy Glushkov #define CONFIG_USB_EHCI_FSL 143c31e1326SValeriy Glushkov 144c31e1326SValeriy Glushkov /* Current USB implementation supports the only USB controller, 145c31e1326SValeriy Glushkov * so we have to choose between the MPH or the DR ones */ 146c31e1326SValeriy Glushkov #if 1 147c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_MPH_USB 148c31e1326SValeriy Glushkov #else 149c31e1326SValeriy Glushkov #define CONFIG_HAS_FSL_DR_USB 150c31e1326SValeriy Glushkov #endif 151c31e1326SValeriy Glushkov 152c31e1326SValeriy Glushkov #endif 153c31e1326SValeriy Glushkov 1547a78f148STimur Tabi /* 1557a78f148STimur Tabi * DDR Setup 1567a78f148STimur Tabi */ 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_83XX_DDR_USES_CS0 1616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x2000 1637a78f148STimur Tabi 164396abba2SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 165396abba2SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 166f64702b7STimur Tabi 167b7be63abSValeriy Glushkov #define CONFIG_VERY_BIG_RAM 168b7be63abSValeriy Glushkov #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 169b7be63abSValeriy Glushkov 17000f792e0SHeiko Schocher #ifdef CONFIG_SYS_I2C 1717a78f148STimur Tabi #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 1727a78f148STimur Tabi #endif 1737a78f148STimur Tabi 174396abba2SJoe Hershberger /* No SPD? Then manually set up DDR parameters */ 175396abba2SJoe Hershberger #ifndef CONFIG_SPD_EEPROM 1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 1772e651b24SJoe Hershberger #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 178396abba2SJoe Hershberger | CSCONFIG_ROW_BIT_13 \ 179396abba2SJoe Hershberger | CSCONFIG_COL_BIT_10) 1807a78f148STimur Tabi 1816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x26242321 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 1837a78f148STimur Tabi #endif 1847a78f148STimur Tabi 1857a78f148STimur Tabi /* 1867a78f148STimur Tabi *Flash on the Local Bus 1877a78f148STimur Tabi */ 1887a78f148STimur Tabi 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 191396abba2SJoe Hershberger /* 127 64KB sectors + 8 8KB sectors per device */ 192396abba2SJoe Hershberger #define CONFIG_SYS_MAX_FLASH_SECT 135 1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 1956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 1967a78f148STimur Tabi 1977a78f148STimur Tabi /* The ITX has two flash chips, but the ITX-GP has only one. To support both 1987a78f148STimur Tabi boards, we say we have two, but don't display a message if we find only one. */ 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 201396abba2SJoe Hershberger #define CONFIG_SYS_FLASH_BANKS_LIST \ 202396abba2SJoe Hershberger {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 2047a78f148STimur Tabi 20589c7784eSTimur Tabi /* Vitesse 7385 */ 20689c7784eSTimur Tabi 20789c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 20889c7784eSTimur Tabi 20989c7784eSTimur Tabi #define CONFIG_TSEC2 21089c7784eSTimur Tabi 21189c7784eSTimur Tabi /* The flash address and size of the VSC7385 firmware image */ 21289c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE 0xFEFFE000 21389c7784eSTimur Tabi #define CONFIG_VSC7385_IMAGE_SIZE 8192 21489c7784eSTimur Tabi 21589c7784eSTimur Tabi #endif 21689c7784eSTimur Tabi 2177a78f148STimur Tabi /* 2187a78f148STimur Tabi * BRx, ORx, LBLAWBARx, and LBLAWARx 2197a78f148STimur Tabi */ 2207a78f148STimur Tabi 2217a78f148STimur Tabi /* Flash */ 2227a78f148STimur Tabi 2237d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 2247d6a0982SJoe Hershberger | BR_PS_16 \ 2257d6a0982SJoe Hershberger | BR_MS_GPCM \ 2267d6a0982SJoe Hershberger | BR_V) 2277d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 228396abba2SJoe Hershberger | OR_UPM_XAM \ 229396abba2SJoe Hershberger | OR_GPCM_CSNT \ 230396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 231396abba2SJoe Hershberger | OR_GPCM_XACS \ 232396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 2337d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2347d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 235396abba2SJoe Hershberger | OR_GPCM_EAD) 2366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 2377d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 2387a78f148STimur Tabi 2397a78f148STimur Tabi /* Vitesse 7385 */ 2407a78f148STimur Tabi 2416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_VSC7385_BASE 0xF8000000 2427a78f148STimur Tabi 24389c7784eSTimur Tabi #ifdef CONFIG_VSC7385_ENET 24489c7784eSTimur Tabi 2457d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 2467d6a0982SJoe Hershberger | BR_PS_8 \ 2477d6a0982SJoe Hershberger | BR_MS_GPCM \ 2487d6a0982SJoe Hershberger | BR_V) 249396abba2SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 250396abba2SJoe Hershberger | OR_GPCM_CSNT \ 251396abba2SJoe Hershberger | OR_GPCM_XACS \ 252396abba2SJoe Hershberger | OR_GPCM_SCY_15 \ 253396abba2SJoe Hershberger | OR_GPCM_SETA \ 2547d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2557d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 256396abba2SJoe Hershberger | OR_GPCM_EAD) 2577a78f148STimur Tabi 2586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 2596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2607a78f148STimur Tabi 2617a78f148STimur Tabi #endif 2627a78f148STimur Tabi 2637a78f148STimur Tabi /* LED */ 2647a78f148STimur Tabi 2656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LED_BASE 0xF9000000 2667d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 2677d6a0982SJoe Hershberger | BR_PS_8 \ 2687d6a0982SJoe Hershberger | BR_MS_GPCM \ 2697d6a0982SJoe Hershberger | BR_V) 270396abba2SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 271396abba2SJoe Hershberger | OR_GPCM_CSNT \ 272396abba2SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 273396abba2SJoe Hershberger | OR_GPCM_XACS \ 274396abba2SJoe Hershberger | OR_GPCM_SCY_9 \ 2757d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2767d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 277396abba2SJoe Hershberger | OR_GPCM_EAD) 2787a78f148STimur Tabi 2797a78f148STimur Tabi /* Compact Flash */ 2807a78f148STimur Tabi 2817a78f148STimur Tabi #ifdef CONFIG_COMPACT_FLASH 2827a78f148STimur Tabi 2836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CF_BASE 0xF0000000 2847a78f148STimur Tabi 285396abba2SJoe Hershberger #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 286396abba2SJoe Hershberger | BR_PS_16 \ 287396abba2SJoe Hershberger | BR_MS_UPMA \ 288396abba2SJoe Hershberger | BR_V) 2896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 2907a78f148STimur Tabi 2916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 2937a78f148STimur Tabi 2947a78f148STimur Tabi #endif 2957a78f148STimur Tabi 2967a78f148STimur Tabi /* 2977a78f148STimur Tabi * U-Boot memory configuration 2987a78f148STimur Tabi */ 29914d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 3002ad6b513STimur Tabi 3016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 3026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_RAMBOOT 3032ad6b513STimur Tabi #else 3046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_RAMBOOT 3052ad6b513STimur Tabi #endif 3062ad6b513STimur Tabi 3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 308396abba2SJoe Hershberger #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 309553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 3102ad6b513STimur Tabi 311396abba2SJoe Hershberger #define CONFIG_SYS_GBL_DATA_OFFSET \ 312396abba2SJoe Hershberger (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 3142ad6b513STimur Tabi 3156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 31616c8c170SKevin Hao #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 317c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 3182ad6b513STimur Tabi 3192ad6b513STimur Tabi /* 3202ad6b513STimur Tabi * Local Bus LCRR and LBCR regs 3212ad6b513STimur Tabi * LCRR: DLL bypass, Clock divider is 4 3222ad6b513STimur Tabi * External Local Bus rate is 3232ad6b513STimur Tabi * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 3242ad6b513STimur Tabi */ 325c7190f02SKim Phillips #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 326c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 3276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LBC_LBCR 0x00000000 3282ad6b513STimur Tabi 329396abba2SJoe Hershberger /* LB sdram refresh timer, about 6us */ 330396abba2SJoe Hershberger #define CONFIG_SYS_LBC_LSRT 0x32000000 331396abba2SJoe Hershberger /* LB refresh timer prescal, 266MHz/32*/ 332396abba2SJoe Hershberger #define CONFIG_SYS_LBC_MRTPR 0x20000000 3332ad6b513STimur Tabi 3342ad6b513STimur Tabi /* 3352ad6b513STimur Tabi * Serial Port 3362ad6b513STimur Tabi */ 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 3402ad6b513STimur Tabi 3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 3422ad6b513STimur Tabi {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 3432ad6b513STimur Tabi 34483302fb8SSimon Glass #define CONSOLE ttyS0 3457a78f148STimur Tabi 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3482ad6b513STimur Tabi 3497a78f148STimur Tabi /* 3507a78f148STimur Tabi * PCI 3517a78f148STimur Tabi */ 3522ad6b513STimur Tabi #ifdef CONFIG_PCI 353842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 3542ad6b513STimur Tabi 3552ad6b513STimur Tabi #define CONFIG_MPC83XX_PCI2 3562ad6b513STimur Tabi 3572ad6b513STimur Tabi /* 3582ad6b513STimur Tabi * General PCI 3592ad6b513STimur Tabi * Addresses are mapped 1-1. 3602ad6b513STimur Tabi */ 3616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 3626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 3636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 364396abba2SJoe Hershberger #define CONFIG_SYS_PCI1_MMIO_BASE \ 365396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 3666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 3676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 3686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 3712ad6b513STimur Tabi 3722ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 373396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MEM_BASE \ 374396abba2SJoe Hershberger (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 3756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 377396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_MMIO_BASE \ 378396abba2SJoe Hershberger (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 3796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 382396abba2SJoe Hershberger #define CONFIG_SYS_PCI2_IO_PHYS \ 383396abba2SJoe Hershberger (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 3846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 3852ad6b513STimur Tabi #endif 3862ad6b513STimur Tabi 3872ad6b513STimur Tabi #ifndef CONFIG_PCI_PNP 3882ad6b513STimur Tabi #define PCI_ENET0_IOADDR 0x00000000 3896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 3902ad6b513STimur Tabi #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 3912ad6b513STimur Tabi #endif 3922ad6b513STimur Tabi 3932ad6b513STimur Tabi #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 3942ad6b513STimur Tabi 3952ad6b513STimur Tabi #endif 3962ad6b513STimur Tabi 3972ae18241SWolfgang Denk #define CONFIG_PCI_66M 3982ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 3997a78f148STimur Tabi #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 4007a78f148STimur Tabi #else 4017a78f148STimur Tabi #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 4027a78f148STimur Tabi #endif 4037a78f148STimur Tabi 4042ad6b513STimur Tabi /* TSEC */ 4052ad6b513STimur Tabi 4062ad6b513STimur Tabi #ifdef CONFIG_TSEC_ENET 407255a3577SKim Phillips #define CONFIG_TSEC1 4082ad6b513STimur Tabi 409255a3577SKim Phillips #ifdef CONFIG_TSEC1 41010327dc5SAndy Fleming #define CONFIG_HAS_ETH0 411255a3577SKim Phillips #define CONFIG_TSEC1_NAME "TSEC0" 4126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC1_OFFSET 0x24000 4132ad6b513STimur Tabi #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 4142ad6b513STimur Tabi #define TSEC1_PHYIDX 0 4153a79013eSAndy Fleming #define TSEC1_FLAGS TSEC_GIGABIT 4162ad6b513STimur Tabi #endif 4172ad6b513STimur Tabi 418255a3577SKim Phillips #ifdef CONFIG_TSEC2 4197a78f148STimur Tabi #define CONFIG_HAS_ETH1 420255a3577SKim Phillips #define CONFIG_TSEC2_NAME "TSEC1" 4216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_TSEC2_OFFSET 0x25000 42289c7784eSTimur Tabi 4232ad6b513STimur Tabi #define TSEC2_PHY_ADDR 4 4242ad6b513STimur Tabi #define TSEC2_PHYIDX 0 4253a79013eSAndy Fleming #define TSEC2_FLAGS TSEC_GIGABIT 4262ad6b513STimur Tabi #endif 4272ad6b513STimur Tabi 4282ad6b513STimur Tabi #define CONFIG_ETHPRIME "Freescale TSEC" 4292ad6b513STimur Tabi 4302ad6b513STimur Tabi #endif 4312ad6b513STimur Tabi 4322ad6b513STimur Tabi /* 4332ad6b513STimur Tabi * Environment 4342ad6b513STimur Tabi */ 4357a78f148STimur Tabi #define CONFIG_ENV_OVERWRITE 4367a78f148STimur Tabi 4376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_RAMBOOT 438396abba2SJoe Hershberger #define CONFIG_ENV_ADDR \ 439396abba2SJoe Hershberger (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 4400e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 4410e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4422ad6b513STimur Tabi #else 4436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 4440e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4452ad6b513STimur Tabi #endif 4462ad6b513STimur Tabi 4472ad6b513STimur Tabi #define CONFIG_LOADS_ECHO /* echo on for serial download */ 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 4492ad6b513STimur Tabi 4508ea5499aSJon Loeliger /* 451659e2f67SJon Loeliger * BOOTP options 452659e2f67SJon Loeliger */ 453659e2f67SJon Loeliger #define CONFIG_BOOTP_BOOTFILESIZE 454659e2f67SJon Loeliger 4552ad6b513STimur Tabi /* Watchdog */ 4562ad6b513STimur Tabi #undef CONFIG_WATCHDOG /* watchdog disabled */ 4572ad6b513STimur Tabi 4582ad6b513STimur Tabi /* 4592ad6b513STimur Tabi * Miscellaneous configurable options 4602ad6b513STimur Tabi */ 4617a78f148STimur Tabi 4626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 46305f91a65SKim Phillips #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 4647a78f148STimur Tabi 4652ad6b513STimur Tabi /* 4662ad6b513STimur Tabi * For booting Linux, the board info and command line data 4679f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 4682ad6b513STimur Tabi * the maximum mapped by the Linux kernel during initialization. 4692ad6b513STimur Tabi */ 470396abba2SJoe Hershberger /* Initial Memory map for Linux*/ 471396abba2SJoe Hershberger #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 47263865278SKevin Hao #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 4732ad6b513STimur Tabi 4746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_LOW (\ 4752ad6b513STimur Tabi HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 4762ad6b513STimur Tabi HRCWL_DDR_TO_SCB_CLK_1X1 |\ 4772ad6b513STimur Tabi HRCWL_CSB_TO_CLKIN_4X1 |\ 4782ad6b513STimur Tabi HRCWL_VCO_1X2 |\ 4792ad6b513STimur Tabi HRCWL_CORE_TO_CSB_2X1) 4802ad6b513STimur Tabi 4816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_LOWBOOT 4826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 4832ad6b513STimur Tabi HRCWH_PCI_HOST |\ 4847a78f148STimur Tabi HRCWH_32_BIT_PCI |\ 4852ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 4867a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 4872ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 4882ad6b513STimur Tabi HRCWH_FROM_0X00000100 |\ 4892ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 4902ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 4912ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 4922ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 4932ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 4942ad6b513STimur Tabi #else 4956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HRCW_HIGH (\ 4962ad6b513STimur Tabi HRCWH_PCI_HOST |\ 4972ad6b513STimur Tabi HRCWH_32_BIT_PCI |\ 4982ad6b513STimur Tabi HRCWH_PCI1_ARBITER_ENABLE |\ 4997a78f148STimur Tabi HRCWH_PCI2_ARBITER_ENABLE |\ 5002ad6b513STimur Tabi HRCWH_CORE_ENABLE |\ 5012ad6b513STimur Tabi HRCWH_FROM_0XFFF00100 |\ 5022ad6b513STimur Tabi HRCWH_BOOTSEQ_DISABLE |\ 5032ad6b513STimur Tabi HRCWH_SW_WATCHDOG_DISABLE |\ 5042ad6b513STimur Tabi HRCWH_ROM_LOC_LOCAL_16BIT |\ 5052ad6b513STimur Tabi HRCWH_TSEC1M_IN_GMII |\ 5062ad6b513STimur Tabi HRCWH_TSEC2M_IN_GMII) 5072ad6b513STimur Tabi #endif 5082ad6b513STimur Tabi 5097a78f148STimur Tabi /* 5107a78f148STimur Tabi * System performance 5117a78f148STimur Tabi */ 5126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 5136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 5146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 5156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 5166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 5176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 518c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 519c31e1326SValeriy Glushkov #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 5202ad6b513STimur Tabi 5217a78f148STimur Tabi /* 5227a78f148STimur Tabi * System IO Config 5237a78f148STimur Tabi */ 524396abba2SJoe Hershberger /* Needed for gigabit to work on TSEC 1 */ 525396abba2SJoe Hershberger #define CONFIG_SYS_SICRH SICRH_TSOBI1 526396abba2SJoe Hershberger /* USB DR as device + USB MPH as host */ 527396abba2SJoe Hershberger #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 5282ad6b513STimur Tabi 5291a2e203bSKim Phillips #define CONFIG_SYS_HID0_INIT 0x00000000 5301a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 5312ad6b513STimur Tabi 5326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HID2 HID2_HBE 53331d82672SBecky Bruce #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 5342ad6b513STimur Tabi 5357a78f148STimur Tabi /* DDR */ 536396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 53772cd4087SJoe Hershberger | BATL_PP_RW \ 538396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 539396abba2SJoe Hershberger #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 540396abba2SJoe Hershberger | BATU_BL_256M \ 541396abba2SJoe Hershberger | BATU_VS \ 542396abba2SJoe Hershberger | BATU_VP) 5432ad6b513STimur Tabi 5447a78f148STimur Tabi /* PCI */ 5452ad6b513STimur Tabi #ifdef CONFIG_PCI 546396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 54772cd4087SJoe Hershberger | BATL_PP_RW \ 548396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 549396abba2SJoe Hershberger #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 550396abba2SJoe Hershberger | BATU_BL_256M \ 551396abba2SJoe Hershberger | BATU_VS \ 552396abba2SJoe Hershberger | BATU_VP) 553396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 55472cd4087SJoe Hershberger | BATL_PP_RW \ 555396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 556396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 557396abba2SJoe Hershberger #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 558396abba2SJoe Hershberger | BATU_BL_256M \ 559396abba2SJoe Hershberger | BATU_VS \ 560396abba2SJoe Hershberger | BATU_VP) 5612ad6b513STimur Tabi #else 5626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1L 0 5636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT1U 0 5646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2L 0 5656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT2U 0 5662ad6b513STimur Tabi #endif 5672ad6b513STimur Tabi 5682ad6b513STimur Tabi #ifdef CONFIG_MPC83XX_PCI2 569396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 57072cd4087SJoe Hershberger | BATL_PP_RW \ 571396abba2SJoe Hershberger | BATL_MEMCOHERENCE) 572396abba2SJoe Hershberger #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 573396abba2SJoe Hershberger | BATU_BL_256M \ 574396abba2SJoe Hershberger | BATU_VS \ 575396abba2SJoe Hershberger | BATU_VP) 576396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 57772cd4087SJoe Hershberger | BATL_PP_RW \ 578396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 579396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 580396abba2SJoe Hershberger #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 581396abba2SJoe Hershberger | BATU_BL_256M \ 582396abba2SJoe Hershberger | BATU_VS \ 583396abba2SJoe Hershberger | BATU_VP) 5842ad6b513STimur Tabi #else 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3L 0 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT3U 0 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4L 0 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT4U 0 5892ad6b513STimur Tabi #endif 5902ad6b513STimur Tabi 5912ad6b513STimur Tabi /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 592396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 59372cd4087SJoe Hershberger | BATL_PP_RW \ 594396abba2SJoe Hershberger | BATL_CACHEINHIBIT \ 595396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 596396abba2SJoe Hershberger #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 597396abba2SJoe Hershberger | BATU_BL_256M \ 598396abba2SJoe Hershberger | BATU_VS \ 599396abba2SJoe Hershberger | BATU_VP) 6002ad6b513STimur Tabi 6012ad6b513STimur Tabi /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 602396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 \ 60372cd4087SJoe Hershberger | BATL_PP_RW \ 604396abba2SJoe Hershberger | BATL_MEMCOHERENCE \ 605396abba2SJoe Hershberger | BATL_GUARDEDSTORAGE) 606396abba2SJoe Hershberger #define CONFIG_SYS_IBAT6U (0xF0000000 \ 607396abba2SJoe Hershberger | BATU_BL_256M \ 608396abba2SJoe Hershberger | BATU_VS \ 609396abba2SJoe Hershberger | BATU_VP) 6102ad6b513STimur Tabi 6116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7L 0 6126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IBAT7U 0 6132ad6b513STimur Tabi 6146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 6156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 6166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 6176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 6186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 6196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 6216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 6226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 6246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 6256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 6266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 6276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 6286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 6296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 6302ad6b513STimur Tabi 6318ea5499aSJon Loeliger #if defined(CONFIG_CMD_KGDB) 6322ad6b513STimur Tabi #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 6332ad6b513STimur Tabi #endif 6342ad6b513STimur Tabi 6352ad6b513STimur Tabi /* 6362ad6b513STimur Tabi * Environment Configuration 6372ad6b513STimur Tabi */ 6382ad6b513STimur Tabi #define CONFIG_ENV_OVERWRITE 6392ad6b513STimur Tabi 640396abba2SJoe Hershberger #define CONFIG_NETDEV "eth0" 6412ad6b513STimur Tabi 6427a78f148STimur Tabi /* Default path and filenames */ 6438b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/nfsroot/rootfs" 644b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 645396abba2SJoe Hershberger /* U-Boot image on TFTP server */ 646396abba2SJoe Hershberger #define CONFIG_UBOOTPATH "u-boot.bin" 6472ad6b513STimur Tabi 6487a78f148STimur Tabi #ifdef CONFIG_MPC8349ITX 649396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitx.dtb" 6502ad6b513STimur Tabi #else 651396abba2SJoe Hershberger #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 6522ad6b513STimur Tabi #endif 6532ad6b513STimur Tabi 6547a78f148STimur Tabi 6552ad6b513STimur Tabi #define CONFIG_EXTRA_ENV_SETTINGS \ 65683302fb8SSimon Glass "console=" __stringify(CONSOLE) "\0" \ 657396abba2SJoe Hershberger "netdev=" CONFIG_NETDEV "\0" \ 658396abba2SJoe Hershberger "uboot=" CONFIG_UBOOTPATH "\0" \ 6597a78f148STimur Tabi "tftpflash=tftpboot $loadaddr $uboot; " \ 6605368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 6615368c55dSMarek Vasut " +$filesize; " \ 6625368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 6635368c55dSMarek Vasut " +$filesize; " \ 6645368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6655368c55dSMarek Vasut " $filesize; " \ 6665368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 6675368c55dSMarek Vasut " +$filesize; " \ 6685368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6695368c55dSMarek Vasut " $filesize\0" \ 67005f91a65SKim Phillips "fdtaddr=780000\0" \ 671396abba2SJoe Hershberger "fdtfile=" CONFIG_FDTFILE "\0" 672bf0b542dSKim Phillips 673bf0b542dSKim Phillips #define CONFIG_NFSBOOTCOMMAND \ 6747a78f148STimur Tabi "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 675bf0b542dSKim Phillips " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 6767a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 677bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 678bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 679bf0b542dSKim Phillips "bootm $loadaddr - $fdtaddr" 680bf0b542dSKim Phillips 681bf0b542dSKim Phillips #define CONFIG_RAMBOOTCOMMAND \ 682bf0b542dSKim Phillips "setenv bootargs root=/dev/ram rw" \ 6837a78f148STimur Tabi " console=$console,$baudrate $othbootargs; " \ 684bf0b542dSKim Phillips "tftp $ramdiskaddr $ramdiskfile;" \ 685bf0b542dSKim Phillips "tftp $loadaddr $bootfile;" \ 686bf0b542dSKim Phillips "tftp $fdtaddr $fdtfile;" \ 687bf0b542dSKim Phillips "bootm $loadaddr $ramdiskaddr $fdtaddr" 6882ad6b513STimur Tabi 6892ad6b513STimur Tabi #endif 690