1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 25fb17030SIlya Yanok /* 35fb17030SIlya Yanok * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 45fb17030SIlya Yanok * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 55fb17030SIlya Yanok * 65fb17030SIlya Yanok */ 75fb17030SIlya Yanok 85fb17030SIlya Yanok #ifndef __CONFIG_H 95fb17030SIlya Yanok #define __CONFIG_H 105fb17030SIlya Yanok 115fb17030SIlya Yanok /* 125fb17030SIlya Yanok * High Level Configuration Options 135fb17030SIlya Yanok */ 145fb17030SIlya Yanok #define CONFIG_E300 1 /* E300 family */ 158afad91fSGerlando Falauto #define CONFIG_MPC830x 1 /* MPC830x family */ 165fb17030SIlya Yanok #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 175fb17030SIlya Yanok 18db1fc7d2SIra W. Snyder #ifdef CONFIG_MMC 19db1fc7d2SIra W. Snyder #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 20db1fc7d2SIra W. Snyder #define CONFIG_SYS_FSL_ESDHC_USE_PIO 21db1fc7d2SIra W. Snyder #endif 22db1fc7d2SIra W. Snyder 235fb17030SIlya Yanok /* 245fb17030SIlya Yanok * On-board devices 255fb17030SIlya Yanok * 265fb17030SIlya Yanok * TSEC1 is SoC TSEC 275fb17030SIlya Yanok * TSEC2 is VSC switch 285fb17030SIlya Yanok */ 295fb17030SIlya Yanok #define CONFIG_TSEC1 305fb17030SIlya Yanok #define CONFIG_VSC7385_ENET 315fb17030SIlya Yanok 325fb17030SIlya Yanok /* 335fb17030SIlya Yanok * System Clock Setup 345fb17030SIlya Yanok */ 355fb17030SIlya Yanok #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 365fb17030SIlya Yanok #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 375fb17030SIlya Yanok 385fb17030SIlya Yanok /* 395fb17030SIlya Yanok * Hardware Reset Configuration Word 405fb17030SIlya Yanok * if CLKIN is 66.66MHz, then 415fb17030SIlya Yanok * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 425fb17030SIlya Yanok * We choose the A type silicon as default, so the core is 400Mhz. 435fb17030SIlya Yanok */ 445fb17030SIlya Yanok #define CONFIG_SYS_HRCW_LOW (\ 455fb17030SIlya Yanok HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 465fb17030SIlya Yanok HRCWL_DDR_TO_SCB_CLK_2X1 |\ 475fb17030SIlya Yanok HRCWL_SVCOD_DIV_2 |\ 485fb17030SIlya Yanok HRCWL_CSB_TO_CLKIN_4X1 |\ 495fb17030SIlya Yanok HRCWL_CORE_TO_CSB_3X1) 505fb17030SIlya Yanok /* 515fb17030SIlya Yanok * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 525fb17030SIlya Yanok * in 8308's HRCWH according to the manual, but original Freescale's 535fb17030SIlya Yanok * code has them and I've expirienced some problems using the board 545fb17030SIlya Yanok * with BDI3000 attached when I've tried to set these bits to zero 555fb17030SIlya Yanok * (UART doesn't work after the 'reset run' command). 565fb17030SIlya Yanok */ 575fb17030SIlya Yanok #define CONFIG_SYS_HRCW_HIGH (\ 585fb17030SIlya Yanok HRCWH_PCI_HOST |\ 595fb17030SIlya Yanok HRCWH_PCI1_ARBITER_ENABLE |\ 605fb17030SIlya Yanok HRCWH_CORE_ENABLE |\ 615fb17030SIlya Yanok HRCWH_FROM_0X00000100 |\ 625fb17030SIlya Yanok HRCWH_BOOTSEQ_DISABLE |\ 635fb17030SIlya Yanok HRCWH_SW_WATCHDOG_DISABLE |\ 645fb17030SIlya Yanok HRCWH_ROM_LOC_LOCAL_16BIT |\ 655fb17030SIlya Yanok HRCWH_RL_EXT_LEGACY |\ 665fb17030SIlya Yanok HRCWH_TSEC1M_IN_RGMII |\ 675fb17030SIlya Yanok HRCWH_TSEC2M_IN_RGMII |\ 685fb17030SIlya Yanok HRCWH_BIG_ENDIAN) 695fb17030SIlya Yanok 705fb17030SIlya Yanok /* 715fb17030SIlya Yanok * System IO Config 725fb17030SIlya Yanok */ 7365ea7589SIlya Yanok #define CONFIG_SYS_SICRH (\ 7465ea7589SIlya Yanok SICRH_ESDHC_A_SD |\ 7565ea7589SIlya Yanok SICRH_ESDHC_B_SD |\ 7665ea7589SIlya Yanok SICRH_ESDHC_C_SD |\ 7765ea7589SIlya Yanok SICRH_GPIO_A_TSEC2 |\ 7865ea7589SIlya Yanok SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ 7965ea7589SIlya Yanok SICRH_IEEE1588_A_GPIO |\ 8065ea7589SIlya Yanok SICRH_USB |\ 8165ea7589SIlya Yanok SICRH_GTM_GPIO |\ 8265ea7589SIlya Yanok SICRH_IEEE1588_B_GPIO |\ 8365ea7589SIlya Yanok SICRH_ETSEC2_CRS |\ 8465ea7589SIlya Yanok SICRH_GPIOSEL_1 |\ 8565ea7589SIlya Yanok SICRH_TMROBI_V3P3 |\ 8665ea7589SIlya Yanok SICRH_TSOBI1_V2P5 |\ 8765ea7589SIlya Yanok SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ 8865ea7589SIlya Yanok #define CONFIG_SYS_SICRL (\ 8965ea7589SIlya Yanok SICRL_SPI_PF0 |\ 9065ea7589SIlya Yanok SICRL_UART_PF0 |\ 9165ea7589SIlya Yanok SICRL_IRQ_PF0 |\ 9265ea7589SIlya Yanok SICRL_I2C2_PF0 |\ 9365ea7589SIlya Yanok SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ 945fb17030SIlya Yanok 955fb17030SIlya Yanok /* 965fb17030SIlya Yanok * IMMR new address 975fb17030SIlya Yanok */ 985fb17030SIlya Yanok #define CONFIG_SYS_IMMR 0xE0000000 995fb17030SIlya Yanok 1005fb17030SIlya Yanok /* 1015fb17030SIlya Yanok * SERDES 1025fb17030SIlya Yanok */ 1035fb17030SIlya Yanok #define CONFIG_FSL_SERDES 1045fb17030SIlya Yanok #define CONFIG_FSL_SERDES1 0xe3000 1055fb17030SIlya Yanok 1065fb17030SIlya Yanok /* 1075fb17030SIlya Yanok * Arbiter Setup 1085fb17030SIlya Yanok */ 1095fb17030SIlya Yanok #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 1105fb17030SIlya Yanok #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 1115fb17030SIlya Yanok #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 1125fb17030SIlya Yanok 1135fb17030SIlya Yanok /* 1145fb17030SIlya Yanok * DDR Setup 1155fb17030SIlya Yanok */ 1165fb17030SIlya Yanok #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 1175fb17030SIlya Yanok #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 1185fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1195fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 1205fb17030SIlya Yanok #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 1215fb17030SIlya Yanok | DDRCDR_PZ_LOZ \ 1225fb17030SIlya Yanok | DDRCDR_NZ_LOZ \ 1235fb17030SIlya Yanok | DDRCDR_ODT \ 1245fb17030SIlya Yanok | DDRCDR_Q_DRN) 1255fb17030SIlya Yanok /* 0x7b880001 */ 1265fb17030SIlya Yanok /* 1275fb17030SIlya Yanok * Manually set up DDR parameters 1285fb17030SIlya Yanok * consist of two chips HY5PS12621BFP-C4 from HYNIX 1295fb17030SIlya Yanok */ 1305fb17030SIlya Yanok 1315fb17030SIlya Yanok #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 1325fb17030SIlya Yanok 1335fb17030SIlya Yanok #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 1345fb17030SIlya Yanok #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 1352fef4020SJoe Hershberger | CSCONFIG_ODT_RD_NEVER \ 1362fef4020SJoe Hershberger | CSCONFIG_ODT_WR_ONLY_CURRENT \ 1375fb17030SIlya Yanok | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 1385fb17030SIlya Yanok /* 0x80010102 */ 1395fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1405fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 1415fb17030SIlya Yanok | (0 << TIMING_CFG0_WRT_SHIFT) \ 1425fb17030SIlya Yanok | (0 << TIMING_CFG0_RRT_SHIFT) \ 1435fb17030SIlya Yanok | (0 << TIMING_CFG0_WWT_SHIFT) \ 1445fb17030SIlya Yanok | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 1455fb17030SIlya Yanok | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 1465fb17030SIlya Yanok | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 1475fb17030SIlya Yanok | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 1485fb17030SIlya Yanok /* 0x00220802 */ 1495fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 1505fb17030SIlya Yanok | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 1515fb17030SIlya Yanok | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 1525fb17030SIlya Yanok | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 1535fb17030SIlya Yanok | (6 << TIMING_CFG1_REFREC_SHIFT) \ 1545fb17030SIlya Yanok | (2 << TIMING_CFG1_WRREC_SHIFT) \ 1555fb17030SIlya Yanok | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 1565fb17030SIlya Yanok | (2 << TIMING_CFG1_WRTORD_SHIFT)) 1575fb17030SIlya Yanok /* 0x27256222 */ 1585fb17030SIlya Yanok #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 1595fb17030SIlya Yanok | (4 << TIMING_CFG2_CPO_SHIFT) \ 1605fb17030SIlya Yanok | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 1615fb17030SIlya Yanok | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 1625fb17030SIlya Yanok | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 1635fb17030SIlya Yanok | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 1645fb17030SIlya Yanok | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 1655fb17030SIlya Yanok /* 0x121048c5 */ 1665fb17030SIlya Yanok #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 1675fb17030SIlya Yanok | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 1685fb17030SIlya Yanok /* 0x03600100 */ 1695fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 1705fb17030SIlya Yanok | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 1712fef4020SJoe Hershberger | SDRAM_CFG_DBW_32) 1725fb17030SIlya Yanok /* 0x43080000 */ 1735fb17030SIlya Yanok 1745fb17030SIlya Yanok #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 1755fb17030SIlya Yanok #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 1765fb17030SIlya Yanok | (0x0232 << SDRAM_MODE_SD_SHIFT)) 1775fb17030SIlya Yanok /* ODT 150ohm CL=3, AL=1 on SDRAM */ 1785fb17030SIlya Yanok #define CONFIG_SYS_DDR_MODE2 0x00000000 1795fb17030SIlya Yanok 1805fb17030SIlya Yanok /* 1815fb17030SIlya Yanok * Memory test 1825fb17030SIlya Yanok */ 1835fb17030SIlya Yanok #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 1845fb17030SIlya Yanok #define CONFIG_SYS_MEMTEST_END 0x07f00000 1855fb17030SIlya Yanok 1865fb17030SIlya Yanok /* 1875fb17030SIlya Yanok * The reserved memory 1885fb17030SIlya Yanok */ 18914d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 1905fb17030SIlya Yanok 19116c8c170SKevin Hao #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 1925fb17030SIlya Yanok #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 1935fb17030SIlya Yanok 1945fb17030SIlya Yanok /* 1955fb17030SIlya Yanok * Initial RAM Base Address Setup 1965fb17030SIlya Yanok */ 1975fb17030SIlya Yanok #define CONFIG_SYS_INIT_RAM_LOCK 1 1985fb17030SIlya Yanok #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 199553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 2005fb17030SIlya Yanok #define CONFIG_SYS_GBL_DATA_OFFSET \ 20125ddd1fbSWolfgang Denk (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2025fb17030SIlya Yanok 2035fb17030SIlya Yanok /* 2045fb17030SIlya Yanok * Local Bus Configuration & Clock Setup 2055fb17030SIlya Yanok */ 2065fb17030SIlya Yanok #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 2075fb17030SIlya Yanok #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 2085fb17030SIlya Yanok #define CONFIG_SYS_LBC_LBCR 0x00040000 2095fb17030SIlya Yanok 2105fb17030SIlya Yanok /* 2115fb17030SIlya Yanok * FLASH on the Local Bus 2125fb17030SIlya Yanok */ 2135fb17030SIlya Yanok #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 2145fb17030SIlya Yanok 2155fb17030SIlya Yanok #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 2165fb17030SIlya Yanok #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 2175fb17030SIlya Yanok 2185fb17030SIlya Yanok /* Window base at flash base */ 2195fb17030SIlya Yanok #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 22065ea7589SIlya Yanok #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 2215fb17030SIlya Yanok 2227d6a0982SJoe Hershberger #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 2237d6a0982SJoe Hershberger | BR_PS_16 /* 16 bit port */ \ 2247d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 2257d6a0982SJoe Hershberger | BR_V) /* valid */ 2267d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 2275fb17030SIlya Yanok | OR_UPM_XAM \ 2285fb17030SIlya Yanok | OR_GPCM_CSNT \ 2295fb17030SIlya Yanok | OR_GPCM_ACS_DIV2 \ 2305fb17030SIlya Yanok | OR_GPCM_XACS \ 2315fb17030SIlya Yanok | OR_GPCM_SCY_15 \ 2327d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2337d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET) 2345fb17030SIlya Yanok 2355fb17030SIlya Yanok #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 2365fb17030SIlya Yanok /* 127 64KB sectors and 8 8KB top sectors per device */ 2375fb17030SIlya Yanok #define CONFIG_SYS_MAX_FLASH_SECT 135 2385fb17030SIlya Yanok 2395fb17030SIlya Yanok #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2405fb17030SIlya Yanok #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 2415fb17030SIlya Yanok 2425fb17030SIlya Yanok /* 2435fb17030SIlya Yanok * NAND Flash on the Local Bus 2445fb17030SIlya Yanok */ 2455fb17030SIlya Yanok #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 2467d6a0982SJoe Hershberger #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 2475fb17030SIlya Yanok #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 2487d6a0982SJoe Hershberger | BR_DECC_CHK_GEN /* Use HW ECC */ \ 2497d6a0982SJoe Hershberger | BR_PS_8 /* 8 bit Port */ \ 2505fb17030SIlya Yanok | BR_MS_FCM /* MSEL = FCM */ \ 2515fb17030SIlya Yanok | BR_V) /* valid */ 2527d6a0982SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ 2535fb17030SIlya Yanok | OR_FCM_CSCT \ 2545fb17030SIlya Yanok | OR_FCM_CST \ 2555fb17030SIlya Yanok | OR_FCM_CHT \ 2565fb17030SIlya Yanok | OR_FCM_SCY_1 \ 2575fb17030SIlya Yanok | OR_FCM_TRLX \ 2585fb17030SIlya Yanok | OR_FCM_EHTR) 2595fb17030SIlya Yanok /* 0xFFFF8396 */ 2605fb17030SIlya Yanok 2615fb17030SIlya Yanok #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 26265ea7589SIlya Yanok #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 2635fb17030SIlya Yanok 2645fb17030SIlya Yanok #ifdef CONFIG_VSC7385_ENET 2655fb17030SIlya Yanok #define CONFIG_TSEC2 2667d6a0982SJoe Hershberger /* VSC7385 Base address on CS2 */ 2675fb17030SIlya Yanok #define CONFIG_SYS_VSC7385_BASE 0xF0000000 2687d6a0982SJoe Hershberger #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 2697d6a0982SJoe Hershberger #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 2707d6a0982SJoe Hershberger | BR_PS_8 /* 8-bit port */ \ 2717d6a0982SJoe Hershberger | BR_MS_GPCM /* MSEL = GPCM */ \ 2727d6a0982SJoe Hershberger | BR_V) /* valid */ 2737d6a0982SJoe Hershberger /* 0xF0000801 */ 2747d6a0982SJoe Hershberger #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ 2757d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 2767d6a0982SJoe Hershberger | OR_GPCM_XACS \ 2777d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 2787d6a0982SJoe Hershberger | OR_GPCM_SETA \ 2797d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 2807d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET) 2817d6a0982SJoe Hershberger /* 0xFFFE09FF */ 2825fb17030SIlya Yanok /* Access window base at VSC7385 base */ 2835fb17030SIlya Yanok #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 2845fb17030SIlya Yanok /* Access window size 128K */ 28565ea7589SIlya Yanok #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 2865fb17030SIlya Yanok /* The flash address and size of the VSC7385 firmware image */ 2875fb17030SIlya Yanok #define CONFIG_VSC7385_IMAGE 0xFE7FE000 2885fb17030SIlya Yanok #define CONFIG_VSC7385_IMAGE_SIZE 8192 2895fb17030SIlya Yanok #endif 2905fb17030SIlya Yanok /* 2915fb17030SIlya Yanok * Serial Port 2925fb17030SIlya Yanok */ 2935fb17030SIlya Yanok #define CONFIG_SYS_NS16550_SERIAL 2945fb17030SIlya Yanok #define CONFIG_SYS_NS16550_REG_SIZE 1 2955fb17030SIlya Yanok #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 2965fb17030SIlya Yanok 2975fb17030SIlya Yanok #define CONFIG_SYS_BAUDRATE_TABLE \ 2985fb17030SIlya Yanok {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 2995fb17030SIlya Yanok 3005fb17030SIlya Yanok #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 3015fb17030SIlya Yanok #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 3025fb17030SIlya Yanok 3035fb17030SIlya Yanok /* I2C */ 30400f792e0SHeiko Schocher #define CONFIG_SYS_I2C 30500f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 30600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 30700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 30800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 30900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 31000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 31100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 31200f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 3135fb17030SIlya Yanok 314ea1ea54eSIra W. Snyder /* 315ea1ea54eSIra W. Snyder * SPI on header J8 316ea1ea54eSIra W. Snyder * 317ea1ea54eSIra W. Snyder * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 318ea1ea54eSIra W. Snyder * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 319ea1ea54eSIra W. Snyder */ 320ea1ea54eSIra W. Snyder #ifdef CONFIG_MPC8XXX_SPI 321ea1ea54eSIra W. Snyder #define CONFIG_USE_SPIFLASH 322ea1ea54eSIra W. Snyder #endif 3235fb17030SIlya Yanok 3245fb17030SIlya Yanok /* 3255fb17030SIlya Yanok * Board info - revision and where boot from 3265fb17030SIlya Yanok */ 3275fb17030SIlya Yanok #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 3285fb17030SIlya Yanok 3295fb17030SIlya Yanok /* 3305fb17030SIlya Yanok * Config on-board RTC 3315fb17030SIlya Yanok */ 3325fb17030SIlya Yanok #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 3335fb17030SIlya Yanok #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 3345fb17030SIlya Yanok 3355fb17030SIlya Yanok /* 3365fb17030SIlya Yanok * General PCI 3375fb17030SIlya Yanok * Addresses are mapped 1-1. 3385fb17030SIlya Yanok */ 3395fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_BASE 0xA0000000 3405fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 3415fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 3425fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 3435fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 3445fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 3455fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 3465fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 3475fb17030SIlya Yanok #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 3485fb17030SIlya Yanok 34965ea7589SIlya Yanok /* enable PCIE clock */ 35065ea7589SIlya Yanok #define CONFIG_SYS_SCCR_PCIEXP1CM 1 3515fb17030SIlya Yanok 352842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 3535fb17030SIlya Yanok #define CONFIG_PCIE 3545fb17030SIlya Yanok 3555fb17030SIlya Yanok #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 3565fb17030SIlya Yanok #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 3575fb17030SIlya Yanok 3585fb17030SIlya Yanok /* 3595fb17030SIlya Yanok * TSEC 3605fb17030SIlya Yanok */ 3615fb17030SIlya Yanok #define CONFIG_SYS_TSEC1_OFFSET 0x24000 3625fb17030SIlya Yanok #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 3635fb17030SIlya Yanok #define CONFIG_SYS_TSEC2_OFFSET 0x25000 3645fb17030SIlya Yanok #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 3655fb17030SIlya Yanok 3665fb17030SIlya Yanok /* 3675fb17030SIlya Yanok * TSEC ethernet configuration 3685fb17030SIlya Yanok */ 3695fb17030SIlya Yanok #define CONFIG_TSEC1_NAME "eTSEC0" 3705fb17030SIlya Yanok #define CONFIG_TSEC2_NAME "eTSEC1" 3715fb17030SIlya Yanok #define TSEC1_PHY_ADDR 2 3725fb17030SIlya Yanok #define TSEC2_PHY_ADDR 1 3735fb17030SIlya Yanok #define TSEC1_PHYIDX 0 3745fb17030SIlya Yanok #define TSEC2_PHYIDX 0 3755fb17030SIlya Yanok #define TSEC1_FLAGS TSEC_GIGABIT 3765fb17030SIlya Yanok #define TSEC2_FLAGS TSEC_GIGABIT 3775fb17030SIlya Yanok 3785fb17030SIlya Yanok /* Options are: eTSEC[0-1] */ 3795fb17030SIlya Yanok #define CONFIG_ETHPRIME "eTSEC0" 3805fb17030SIlya Yanok 3815fb17030SIlya Yanok /* 3825fb17030SIlya Yanok * Environment 3835fb17030SIlya Yanok */ 3845fb17030SIlya Yanok #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 3855fb17030SIlya Yanok CONFIG_SYS_MONITOR_LEN) 3865fb17030SIlya Yanok #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 3875fb17030SIlya Yanok #define CONFIG_ENV_SIZE 0x2000 3885fb17030SIlya Yanok #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 3895fb17030SIlya Yanok #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 3905fb17030SIlya Yanok 3915fb17030SIlya Yanok #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 3925fb17030SIlya Yanok #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 3935fb17030SIlya Yanok 3945fb17030SIlya Yanok /* 3955fb17030SIlya Yanok * BOOTP options 3965fb17030SIlya Yanok */ 3975fb17030SIlya Yanok #define CONFIG_BOOTP_BOOTFILESIZE 3985fb17030SIlya Yanok 3995fb17030SIlya Yanok /* 4005fb17030SIlya Yanok * Command line configuration. 4015fb17030SIlya Yanok */ 4025fb17030SIlya Yanok 4035fb17030SIlya Yanok /* 4045fb17030SIlya Yanok * Miscellaneous configurable options 4055fb17030SIlya Yanok */ 4065fb17030SIlya Yanok #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 4075fb17030SIlya Yanok 4085fb17030SIlya Yanok #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 4095fb17030SIlya Yanok 4105fb17030SIlya Yanok /* Boot Argument Buffer Size */ 4115fb17030SIlya Yanok #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 4125fb17030SIlya Yanok 4135fb17030SIlya Yanok /* 4145fb17030SIlya Yanok * For booting Linux, the board info and command line data 4159f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 4165fb17030SIlya Yanok * the maximum mapped by the Linux kernel during initialization. 4175fb17030SIlya Yanok */ 4189f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 41963865278SKevin Hao #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 4205fb17030SIlya Yanok 4215fb17030SIlya Yanok /* 4225fb17030SIlya Yanok * Core HID Setup 4235fb17030SIlya Yanok */ 4245fb17030SIlya Yanok #define CONFIG_SYS_HID0_INIT 0x000000000 4255fb17030SIlya Yanok #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 4265fb17030SIlya Yanok HID0_ENABLE_INSTRUCTION_CACHE | \ 4275fb17030SIlya Yanok HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 4285fb17030SIlya Yanok #define CONFIG_SYS_HID2 HID2_HBE 4295fb17030SIlya Yanok 4305fb17030SIlya Yanok /* 4315fb17030SIlya Yanok * MMU Setup 4325fb17030SIlya Yanok */ 4335fb17030SIlya Yanok 4345fb17030SIlya Yanok /* DDR: cache cacheable */ 43572cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 4365fb17030SIlya Yanok BATL_MEMCOHERENCE) 4375fb17030SIlya Yanok #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 4385fb17030SIlya Yanok BATU_VS | BATU_VP) 4395fb17030SIlya Yanok #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 4405fb17030SIlya Yanok #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 4415fb17030SIlya Yanok 4425fb17030SIlya Yanok /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 44372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 4445fb17030SIlya Yanok BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 4455fb17030SIlya Yanok #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 4465fb17030SIlya Yanok BATU_VP) 4475fb17030SIlya Yanok #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 4485fb17030SIlya Yanok #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 4495fb17030SIlya Yanok 4505fb17030SIlya Yanok /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 45172cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 4525fb17030SIlya Yanok BATL_MEMCOHERENCE) 4535fb17030SIlya Yanok #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 4545fb17030SIlya Yanok BATU_VS | BATU_VP) 45572cd4087SJoe Hershberger #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 4565fb17030SIlya Yanok BATL_CACHEINHIBIT | \ 4575fb17030SIlya Yanok BATL_GUARDEDSTORAGE) 4585fb17030SIlya Yanok #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 4595fb17030SIlya Yanok 4605fb17030SIlya Yanok /* Stack in dcache: cacheable, no memory coherence */ 46172cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 4625fb17030SIlya Yanok #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 4635fb17030SIlya Yanok BATU_VS | BATU_VP) 4645fb17030SIlya Yanok #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 4655fb17030SIlya Yanok #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 4665fb17030SIlya Yanok 4675fb17030SIlya Yanok /* 4685fb17030SIlya Yanok * Environment Configuration 4695fb17030SIlya Yanok */ 4705fb17030SIlya Yanok 4715fb17030SIlya Yanok #define CONFIG_ENV_OVERWRITE 4725fb17030SIlya Yanok 4735fb17030SIlya Yanok #if defined(CONFIG_TSEC_ENET) 4745fb17030SIlya Yanok #define CONFIG_HAS_ETH0 4755fb17030SIlya Yanok #define CONFIG_HAS_ETH1 4765fb17030SIlya Yanok #endif 4775fb17030SIlya Yanok 4785fb17030SIlya Yanok #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 4795fb17030SIlya Yanok 4805fb17030SIlya Yanok 4815fb17030SIlya Yanok #define CONFIG_EXTRA_ENV_SETTINGS \ 4825fb17030SIlya Yanok "netdev=eth0\0" \ 4835fb17030SIlya Yanok "consoledev=ttyS0\0" \ 4845fb17030SIlya Yanok "nfsargs=setenv bootargs root=/dev/nfs rw " \ 4855fb17030SIlya Yanok "nfsroot=${serverip}:${rootpath}\0" \ 4865fb17030SIlya Yanok "ramargs=setenv bootargs root=/dev/ram rw\0" \ 4875fb17030SIlya Yanok "addip=setenv bootargs ${bootargs} " \ 4885fb17030SIlya Yanok "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 4895fb17030SIlya Yanok ":${hostname}:${netdev}:off panic=1\0" \ 4905fb17030SIlya Yanok "addtty=setenv bootargs ${bootargs}" \ 4915fb17030SIlya Yanok " console=${consoledev},${baudrate}\0" \ 4925fb17030SIlya Yanok "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 4935fb17030SIlya Yanok "addmisc=setenv bootargs ${bootargs}\0" \ 4945fb17030SIlya Yanok "kernel_addr=FE080000\0" \ 4955fb17030SIlya Yanok "fdt_addr=FE280000\0" \ 4965fb17030SIlya Yanok "ramdisk_addr=FE290000\0" \ 4975fb17030SIlya Yanok "u-boot=mpc8308rdb/u-boot.bin\0" \ 4985fb17030SIlya Yanok "kernel_addr_r=1000000\0" \ 4995fb17030SIlya Yanok "fdt_addr_r=C00000\0" \ 5005fb17030SIlya Yanok "hostname=mpc8308rdb\0" \ 5015fb17030SIlya Yanok "bootfile=mpc8308rdb/uImage\0" \ 5025fb17030SIlya Yanok "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 5035fb17030SIlya Yanok "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 5045fb17030SIlya Yanok "flash_self=run ramargs addip addtty addmtd addmisc;" \ 5055fb17030SIlya Yanok "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 5065fb17030SIlya Yanok "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 5075fb17030SIlya Yanok "bootm ${kernel_addr} - ${fdt_addr}\0" \ 5085fb17030SIlya Yanok "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 5095fb17030SIlya Yanok "tftp ${fdt_addr_r} ${fdtfile};" \ 5105fb17030SIlya Yanok "run nfsargs addip addtty addmtd addmisc;" \ 5115fb17030SIlya Yanok "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 5125fb17030SIlya Yanok "bootcmd=run flash_self\0" \ 5135fb17030SIlya Yanok "load=tftp ${loadaddr} ${u-boot}\0" \ 51493ea89f0SMarek Vasut "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 51593ea89f0SMarek Vasut " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 5165fb17030SIlya Yanok " +${filesize};cp.b ${fileaddr} " \ 51793ea89f0SMarek Vasut __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 5185fb17030SIlya Yanok "upd=run load update\0" \ 5195fb17030SIlya Yanok 5205fb17030SIlya Yanok #endif /* __CONFIG_H */ 521