/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ |
H A D | ddr.h | 397 BASE_CFG + ICPU_TIMER_CTRL(0)); in sleep_100ns() 430 writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6)); in hal_vcoreiii_ddr_failed() 463 writel(readl(BASE_CFG + ICPU_RESET) | in hal_vcoreiii_ddr_reset_assert() 469 writel(0, BASE_CFG + ICPU_RESET); in hal_vcoreiii_ddr_failed() 494 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), BASE_CFG + ICPU_MEMCTRL_STAT); in hal_vcoreiii_ddr_verified() 509 BASE_CFG + ICPU_MEMCTRL_STAT); in look_for() 549 BASE_CFG + ICPU_MEMCTRL_STAT); in look_past() 663 BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed() 665 BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed() 667 BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed() [all …]
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/openbmc/u-boot/arch/mips/mach-mscc/ |
H A D | reset.c | 16 register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); in _machine_restart() 22 writel(reg, BASE_CFG + ICPU_GENERAL_CTRL); in _machine_restart() 24 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); in _machine_restart() 26 writel(readl(BASE_CFG + ICPU_RESET) | in _machine_restart() 29 BASE_CFG + ICPU_RESET); in _machine_restart() 34 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); in _machine_restart() 43 writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) | in _machine_restart() 45 BASE_CFG + ICPU_MEMCTRL_CTRL); in _machine_restart() 47 while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) & in _machine_restart() 52 writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET); in _machine_restart() [all …]
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H A D | cpu.c | 84 ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG); in mach_cpu_init() 88 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); in mach_cpu_init() 92 ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG); in mach_cpu_init() 97 ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG); in mach_cpu_init() 103 writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0)); in mach_cpu_init() 104 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1)); in mach_cpu_init() 105 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2)); in mach_cpu_init() 106 writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3)); in mach_cpu_init()
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H A D | dram.c | 36 if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) in vcoreiii_ddr_init() 51 clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in vcoreiii_ddr_init() 53 readl(BASE_CFG + ICPU_GENERAL_CTRL); in vcoreiii_ddr_init()
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/openbmc/u-boot/board/mscc/common/ |
H A D | spi.c | 21 BASE_CFG + ICPU_SW_MODE); in external_cs_manage() 22 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in external_cs_manage() 26 writel(0, BASE_CFG + ICPU_SW_MODE); in external_cs_manage() 27 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in external_cs_manage()
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/openbmc/u-boot/board/mscc/ocelot/ |
H A D | ocelot.c | 29 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); in mscc_switch_reset() 55 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r() 56 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in board_early_init_r()
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/openbmc/u-boot/board/mscc/jr2/ |
H A D | jr2.c | 19 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r() 20 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, in board_early_init_r()
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/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/ |
H A D | ocelot.h | 21 #define BASE_CFG ((void __iomem *)0x70000000) macro
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/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/ |
H A D | serval.h | 21 #define BASE_CFG ((void __iomem *)0x70000000) macro
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/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/ |
H A D | jr2.h | 21 #define BASE_CFG ((void __iomem *)0x70000000) macro
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/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/ |
H A D | servalt.h | 21 #define BASE_CFG ((void __iomem *)0x70000000) macro
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/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/ |
H A D | luton.h | 21 #define BASE_CFG ((void __iomem *)0x70000000) macro
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/openbmc/u-boot/board/mscc/servalt/ |
H A D | servalt.c | 17 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
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/openbmc/u-boot/board/mscc/serval/ |
H A D | serval.c | 18 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
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/openbmc/u-boot/board/mscc/luton/ |
H A D | luton.c | 27 writel(0, BASE_CFG + ICPU_SW_MODE); in board_early_init_r()
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