1dd1033e4SGregory CLEMENT // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2dd1033e4SGregory CLEMENT /* 3dd1033e4SGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4dd1033e4SGregory CLEMENT */ 5dd1033e4SGregory CLEMENT 6dd1033e4SGregory CLEMENT #include <common.h> 7dd1033e4SGregory CLEMENT 8dd1033e4SGregory CLEMENT #include <asm/io.h> 9dd1033e4SGregory CLEMENT #include <asm/types.h> 10dd1033e4SGregory CLEMENT 11dd1033e4SGregory CLEMENT #include <mach/tlb.h> 12dd1033e4SGregory CLEMENT #include <mach/ddr.h> 13dd1033e4SGregory CLEMENT 14dd1033e4SGregory CLEMENT DECLARE_GLOBAL_DATA_PTR; 15dd1033e4SGregory CLEMENT vcoreiii_train_bytelane(void)16dd1033e4SGregory CLEMENTstatic inline int vcoreiii_train_bytelane(void) 17dd1033e4SGregory CLEMENT { 18dd1033e4SGregory CLEMENT int ret; 19dd1033e4SGregory CLEMENT 20dd1033e4SGregory CLEMENT ret = hal_vcoreiii_train_bytelane(0); 21dd1033e4SGregory CLEMENT 2205512517SHoratiu Vultur #if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \ 23*1895b87eSHoratiu Vultur defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL) 24dd1033e4SGregory CLEMENT if (ret) 25dd1033e4SGregory CLEMENT return ret; 26dd1033e4SGregory CLEMENT ret = hal_vcoreiii_train_bytelane(1); 276bd8231aSGregory CLEMENT #endif 28dd1033e4SGregory CLEMENT 29dd1033e4SGregory CLEMENT return ret; 30dd1033e4SGregory CLEMENT } 31dd1033e4SGregory CLEMENT vcoreiii_ddr_init(void)32dd1033e4SGregory CLEMENTint vcoreiii_ddr_init(void) 33dd1033e4SGregory CLEMENT { 34dd1033e4SGregory CLEMENT int res; 35dd1033e4SGregory CLEMENT 36dd1033e4SGregory CLEMENT if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) 37dd1033e4SGregory CLEMENT & ICPU_MEMCTRL_STAT_INIT_DONE)) { 38dd1033e4SGregory CLEMENT hal_vcoreiii_init_memctl(); 39dd1033e4SGregory CLEMENT hal_vcoreiii_wait_memctl(); 40dd1033e4SGregory CLEMENT if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane()) 41dd1033e4SGregory CLEMENT hal_vcoreiii_ddr_failed(); 42dd1033e4SGregory CLEMENT } 43dd1033e4SGregory CLEMENT #if (CONFIG_SYS_TEXT_BASE != 0x20000000) 44dd1033e4SGregory CLEMENT res = dram_check(); 45dd1033e4SGregory CLEMENT if (res == 0) 46dd1033e4SGregory CLEMENT hal_vcoreiii_ddr_verified(); 47dd1033e4SGregory CLEMENT else 48dd1033e4SGregory CLEMENT hal_vcoreiii_ddr_failed(); 49dd1033e4SGregory CLEMENT 50dd1033e4SGregory CLEMENT /* Clear boot-mode and read-back to activate/verify */ 51dd1033e4SGregory CLEMENT clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, 52dd1033e4SGregory CLEMENT ICPU_GENERAL_CTRL_BOOT_MODE_ENA); 53dd1033e4SGregory CLEMENT readl(BASE_CFG + ICPU_GENERAL_CTRL); 54dd1033e4SGregory CLEMENT #else 55dd1033e4SGregory CLEMENT res = 0; 56dd1033e4SGregory CLEMENT #endif 57dd1033e4SGregory CLEMENT return res; 58dd1033e4SGregory CLEMENT } 59dd1033e4SGregory CLEMENT print_cpuinfo(void)60dd1033e4SGregory CLEMENTint print_cpuinfo(void) 61dd1033e4SGregory CLEMENT { 62dd1033e4SGregory CLEMENT printf("MSCC VCore-III MIPS 24Kec\n"); 63dd1033e4SGregory CLEMENT 64dd1033e4SGregory CLEMENT return 0; 65dd1033e4SGregory CLEMENT } 66dd1033e4SGregory CLEMENT dram_init(void)67dd1033e4SGregory CLEMENTint dram_init(void) 68dd1033e4SGregory CLEMENT { 69dd1033e4SGregory CLEMENT while (vcoreiii_ddr_init()) 70dd1033e4SGregory CLEMENT ; 71dd1033e4SGregory CLEMENT 72dd1033e4SGregory CLEMENT gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 73dd1033e4SGregory CLEMENT return 0; 74dd1033e4SGregory CLEMENT } 75