1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6 #include <common.h>
7
8 #include <asm/sections.h>
9 #include <asm/io.h>
10
11 #include <asm/reboot.h>
12
_machine_restart(void)13 void _machine_restart(void)
14 {
15 #if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
16 register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
17 /* Set owner */
18 reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
19 reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1);
20 /* Set boot mode */
21 reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA;
22 writel(reg, BASE_CFG + ICPU_GENERAL_CTRL);
23 /* Read back in order to make BOOT mode setting active */
24 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
25 /* Reset CPU only - still executing _here_. but from cache */
26 writel(readl(BASE_CFG + ICPU_RESET) |
27 ICPU_RESET_CORE_RST_CPU_ONLY |
28 ICPU_RESET_CORE_RST_FORCE,
29 BASE_CFG + ICPU_RESET);
30 #elif defined(CONFIG_SOC_SERVAL)
31 register unsigned long i;
32
33 /* Prevent VCore-III from being reset with a global reset */
34 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
35
36 /* Do global reset */
37 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
38
39 for (i = 0; i < 1000; i++)
40 ;
41
42 /* Power down DDR for clean DDR re-training */
43 writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) |
44 ICPU_MEMCTRL_CTRL_PWR_DOWN,
45 BASE_CFG + ICPU_MEMCTRL_CTRL);
46
47 while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
48 ICPU_MEMCTRL_STAT_PWR_DOWN_ACK))
49 ;
50
51 /* Reset VCore-III, only. */
52 writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET);
53 #else /* Luton || Ocelot */
54 register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
55 (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
56
57 /* Make sure VCore is NOT protected from reset */
58 clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
59
60 /* Change to SPI bitbang for SPI reset workaround... */
61 writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
62 ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
63
64 /* Do the global reset */
65 writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
66 #endif
67
68 while (1)
69 ; /* NOP */
70 }
71