Lines Matching refs:BASE_CFG
336 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
340 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
345 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in incr_dly()
348 writel(r + 1, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in incr_dly()
357 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0)); in adjust_dly()
360 writel(r + adjust, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(0)); in adjust_dly()
370 register u32 r = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)) - start; in center_dly()
372 writel(start + (r >> 1), BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in center_dly()
377 setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_FIFO_RST); in memphy_soft_reset()
379 clrbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_FIFO_RST); in memphy_soft_reset()
390 writel(VCOREIII_TIMER_DIVIDER - 1, BASE_CFG + ICPU_TIMER_TICK_DIV); in sleep_100ns()
393 writel(val, BASE_CFG + ICPU_TIMER_VALUE(0)); in sleep_100ns()
397 BASE_CFG + ICPU_TIMER_CTRL(0)); in sleep_100ns()
400 while (readl(BASE_CFG + ICPU_TIMER_VALUE(0)) != 0) in sleep_100ns()
430 writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6)); in hal_vcoreiii_ddr_failed()
459 writel(readl(BASE_CFG + ICPU_MEMPHY_CFG) | in hal_vcoreiii_ddr_reset_assert()
460 ICPU_MEMPHY_CFG_PHY_RST, BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_reset_assert()
463 writel(readl(BASE_CFG + ICPU_RESET) | in hal_vcoreiii_ddr_reset_assert()
464 ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET); in hal_vcoreiii_ddr_reset_assert()
469 writel(0, BASE_CFG + ICPU_RESET); in hal_vcoreiii_ddr_failed()
470 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); in hal_vcoreiii_ddr_failed()
485 register u32 val = readl(BASE_CFG + ICPU_MEMCTRL_CFG); in hal_vcoreiii_ddr_verified()
490 writel(val, BASE_CFG + ICPU_MEMCTRL_CFG); in hal_vcoreiii_ddr_verified()
494 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), BASE_CFG + ICPU_MEMCTRL_STAT); in hal_vcoreiii_ddr_verified()
508 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), in look_for()
509 BASE_CFG + ICPU_MEMCTRL_STAT); in look_for()
520 if (readl(BASE_CFG + ICPU_MEMCTRL_STAT) & in look_for()
548 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), in look_past()
549 BASE_CFG + ICPU_MEMCTRL_STAT); in look_past()
558 if (readl(BASE_CFG + ICPU_MEMCTRL_STAT) & in look_past()
588 dqs_s = readl(BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in hal_vcoreiii_train_bytelane()
617 writel(readl(BASE_CFG + ICPU_MEMCTRL_STAT), in hal_vcoreiii_init_dqs()
618 BASE_CFG + ICPU_MEMCTRL_STAT); in hal_vcoreiii_init_dqs()
621 if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) & in hal_vcoreiii_init_dqs()
649 setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_RST); in hal_vcoreiii_ddr_reset_assert()
650 setbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE); in hal_vcoreiii_ddr_reset_assert()
659 register u32 memphy_cfg = readl(BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed()
663 BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed()
665 BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed()
667 BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_failed()
747 clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE); in hal_vcoreiii_init_memctl()
752 writel(ICPU_MEMPHY_CFG_PHY_SSTL_ENA, BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_init_memctl()
760 ICPU_MEMPHY_ZCAL_ZCAL_ENA, BASE_CFG + ICPU_MEMPHY_ZCAL); in hal_vcoreiii_init_memctl()
763 while (readl(BASE_CFG + ICPU_MEMPHY_ZCAL) & ICPU_MEMPHY_ZCAL_ZCAL_ENA) in hal_vcoreiii_init_memctl()
768 if (readl(BASE_CFG + ICPU_MEMPHY_ZCAL_STAT) in hal_vcoreiii_init_memctl()
773 setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_ODT_OE | in hal_vcoreiii_init_memctl()
777 writel(MSCC_MEMPARM_MEMCFG, BASE_CFG + ICPU_MEMCTRL_CFG); in hal_vcoreiii_init_memctl()
778 writel(MSCC_MEMPARM_PERIOD, BASE_CFG + ICPU_MEMCTRL_REF_PERIOD); in hal_vcoreiii_init_memctl()
782 writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0); in hal_vcoreiii_init_memctl()
784 clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1)); in hal_vcoreiii_init_memctl()
785 setbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, MSCC_MEMPARM_TIMING0); in hal_vcoreiii_init_memctl()
788 writel(MSCC_MEMPARM_TIMING1, BASE_CFG + ICPU_MEMCTRL_TIMING1); in hal_vcoreiii_init_memctl()
789 writel(MSCC_MEMPARM_TIMING2, BASE_CFG + ICPU_MEMCTRL_TIMING2); in hal_vcoreiii_init_memctl()
790 writel(MSCC_MEMPARM_TIMING3, BASE_CFG + ICPU_MEMCTRL_TIMING3); in hal_vcoreiii_init_memctl()
791 writel(MSCC_MEMPARM_MR0, BASE_CFG + ICPU_MEMCTRL_MR0_VAL); in hal_vcoreiii_init_memctl()
792 writel(MSCC_MEMPARM_MR1, BASE_CFG + ICPU_MEMCTRL_MR1_VAL); in hal_vcoreiii_init_memctl()
793 writel(MSCC_MEMPARM_MR2, BASE_CFG + ICPU_MEMCTRL_MR2_VAL); in hal_vcoreiii_init_memctl()
794 writel(MSCC_MEMPARM_MR3, BASE_CFG + ICPU_MEMCTRL_MR3_VAL); in hal_vcoreiii_init_memctl()
801 BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL); in hal_vcoreiii_init_memctl()
808 writel(readl(BASE_CFG + ICPU_GPR(7)) + 1, BASE_CFG + ICPU_GPR(7)); in hal_vcoreiii_init_memctl()
811 BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL); in hal_vcoreiii_init_memctl()
814 writel(0, BASE_CFG + ICPU_MEMCTRL_TERMRES_CTRL); in hal_vcoreiii_init_memctl()
822 writel(ICPU_MEMCTRL_CTRL_INITIALIZE, BASE_CFG + ICPU_MEMCTRL_CTRL); in hal_vcoreiii_wait_memctl()
824 while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) in hal_vcoreiii_wait_memctl()