1*c75c9083SHoratiu Vultur // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*c75c9083SHoratiu Vultur /* 3*c75c9083SHoratiu Vultur * Copyright (c) 2018 Microsemi Coprporation 4*c75c9083SHoratiu Vultur */ 5*c75c9083SHoratiu Vultur 6*c75c9083SHoratiu Vultur #include <common.h> 7*c75c9083SHoratiu Vultur #include <asm/io.h> 8*c75c9083SHoratiu Vultur #include <spi.h> 9*c75c9083SHoratiu Vultur external_cs_manage(struct udevice * dev,bool enable)10*c75c9083SHoratiu Vulturvoid external_cs_manage(struct udevice *dev, bool enable) 11*c75c9083SHoratiu Vultur { 12*c75c9083SHoratiu Vultur u32 cs = spi_chip_select(dev); 13*c75c9083SHoratiu Vultur /* IF_SI0_OWNER, select the owner of the SI interface 14*c75c9083SHoratiu Vultur * Encoding: 0: SI Slave 15*c75c9083SHoratiu Vultur * 1: SI Boot Master 16*c75c9083SHoratiu Vultur * 2: SI Master Controller 17*c75c9083SHoratiu Vultur */ 18*c75c9083SHoratiu Vultur if (!enable) { 19*c75c9083SHoratiu Vultur writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE | 20*c75c9083SHoratiu Vultur ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), 21*c75c9083SHoratiu Vultur BASE_CFG + ICPU_SW_MODE); 22*c75c9083SHoratiu Vultur clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, 23*c75c9083SHoratiu Vultur ICPU_GENERAL_CTRL_IF_SI_OWNER_M, 24*c75c9083SHoratiu Vultur ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); 25*c75c9083SHoratiu Vultur } else { 26*c75c9083SHoratiu Vultur writel(0, BASE_CFG + ICPU_SW_MODE); 27*c75c9083SHoratiu Vultur clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, 28*c75c9083SHoratiu Vultur ICPU_GENERAL_CTRL_IF_SI_OWNER_M, 29*c75c9083SHoratiu Vultur ICPU_GENERAL_CTRL_IF_SI_OWNER(1)); 30*c75c9083SHoratiu Vultur } 31*c75c9083SHoratiu Vultur } 32