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/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dperf_event.c116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
131 [ C(L1I) ] = {
132 [ C(OP_READ) ] = {
146 [ C(LL) ] = {
147 [ C(OP_READ) ] = {
161 [ C(DTLB) ] = {
162 [ C(OP_READ) ] = {
176 [ C(ITLB) ] = {
191 [ C(BPU) ] = {
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dperf_event.c91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
106 [ C(L1I) ] = {
107 [ C(OP_READ) ] = {
121 [ C(LL) ] = {
122 [ C(OP_READ) ] = {
136 [ C(DTLB) ] = {
137 [ C(OP_READ) ] = {
151 [ C(ITLB) ] = {
166 [ C(BPU) ] = {
[all …]
/openbmc/linux/arch/x86/events/zhaoxin/
H A Dcore.c51 [C(L1D)] = {
65 [C(L1I)] = {
79 [C(LL)] = {
93 [C(DTLB)] = {
107 [C(ITLB)] = {
121 [C(BPU)] = {
135 [C(NODE)] = {
155 [C(L1D)] = {
169 [C(L1I)] = {
183 [C(LL)] = {
[all …]
/openbmc/linux/arch/powerpc/perf/
H A Dpower10-pmu.c358 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
359 [C(L1D)] = {
373 [C(L1I)] = {
387 [C(LL)] = {
429 [C(BPU)] = {
459 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
460 [C(L1D)] = {
474 [C(L1I)] = {
488 [C(LL)] = {
530 [C(BPU)] = {
[all …]
H A Dgeneric-compat-pmu.c185 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
186 [ C(L1D) ] = {
187 [ C(OP_READ) ] = {
200 [ C(L1I) ] = {
201 [ C(OP_READ) ] = {
214 [ C(LL) ] = {
228 [ C(DTLB) ] = {
242 [ C(ITLB) ] = {
256 [ C(BPU) ] = {
270 [ C(NODE) ] = {
[all …]
H A Dpower8-pmu.c266 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
267 [ C(L1D) ] = {
268 [ C(OP_READ) ] = {
281 [ C(L1I) ] = {
282 [ C(OP_READ) ] = {
295 [ C(LL) ] = {
309 [ C(DTLB) ] = {
323 [ C(ITLB) ] = {
337 [ C(BPU) ] = {
351 [ C(NODE) ] = {
[all …]
H A Dpower9-pmu.c337 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
338 [ C(L1D) ] = {
339 [ C(OP_READ) ] = {
352 [ C(L1I) ] = {
353 [ C(OP_READ) ] = {
366 [ C(LL) ] = {
380 [ C(DTLB) ] = {
394 [ C(ITLB) ] = {
408 [ C(BPU) ] = {
422 [ C(NODE) ] = {
[all …]
H A De6500-pmu.c35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
53 [C(LL)] = {
55 [C(OP_READ)] = { 0, 0 },
56 [C(OP_WRITE)] = { 0, 0 },
65 [C(DTLB)] = {
71 [C(BPU)] = {
[all …]
H A De500-pmu.c34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
56 [C(OP_READ)] = { 0, 0 },
57 [C(OP_WRITE)] = { 0, 0 },
67 [C(OP_READ)] = { 26, 66 },
68 [C(OP_WRITE)] = { -1, -1 },
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/hddtemp/hddtemp/
H A Dhddtemp.db252 # 10�C below the ambient temperature
264 "SAMSUNG SP(0612|0802|1203|1604|0812|1213|1614)C" 194 C "Samsung SpinPoint P80 series - SATA"
267 "SAMSUNG SP(0812|1213|1614)C" 194 C "Samsung Spinpoint 160G SATA"
269 "SAMSUNG SP2[05]04C" 194 C "Samsung SpinPoint P120 series - SATA"
282 "ST3412A" 0 C "Seagate ST3412A"
283 "ST38641A" 0 C "Seagate ST38641A"
344 "ST3500630NS" 194 C "Seagate"
345 "ST3400632NS" 194 C "Seagate"
350 "ST94019A" 194 C "Seagate ST94019A"
408 #"WDC WD400BB-00GFA0" 0 C ""
[all …]
/openbmc/linux/arch/x86/events/intel/
H A Dp6.c28 [ C(L1D) ] = {
29 [ C(OP_READ) ] = {
33 [ C(OP_WRITE) ] = {
42 [ C(L1I ) ] = {
43 [ C(OP_READ) ] = {
56 [ C(LL ) ] = {
57 [ C(OP_READ) ] = {
70 [ C(DTLB) ] = {
71 [ C(OP_READ) ] = {
84 [ C(ITLB) ] = {
[all …]
H A Dknc.c26 [ C(L1D) ] = {
27 [ C(OP_READ) ] = {
36 [ C(OP_WRITE) ] = {
45 [ C(L1I ) ] = {
46 [ C(OP_READ) ] = {
59 [ C(LL ) ] = {
60 [ C(OP_READ) ] = {
73 [ C(DTLB) ] = {
74 [ C(OP_READ) ] = {
89 [ C(ITLB) ] = {
[all …]
H A Dcore.c1865 [C(LL)] = {
1927 [C(LL)] = {
6198 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6225 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6256 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6434 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
6436 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
6438 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
6440 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()
6556 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dperf_event_v7.c192 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
193 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
195 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
196 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
236 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
239 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
518 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS,
524 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
526 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
527 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
[all …]
/openbmc/linux/tools/testing/selftests/bpf/progs/
H A Dtest_verif_scale2.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dtest_verif_scale3.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dtest_verif_scale1.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dcore_kern.c85 #define C do { \ in balancer_ingress() macro
99 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
/openbmc/linux/arch/sparc/kernel/
H A Dperf_event.c221 [C(L1D)] = {
235 [C(L1I)] = {
249 [C(LL)] = {
291 [C(BPU)] = {
359 [C(L1D)] = {
373 [C(L1I)] = {
387 [C(LL)] = {
429 [C(BPU)] = {
494 [C(L1D)] = {
522 [C(LL)] = {
[all …]
/openbmc/linux/drivers/perf/
H A Driscv_pmu_sbi.c126 [C(L1D)] = {
129 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
131 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
135 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
137 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
149 C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
150 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
166 [C(LL)] = {
169 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
171 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dperf_event_mipsxx.c1010 [C(L1D)] = {
1026 [C(L1I)] = {
1043 [C(LL)] = {
1073 [C(BPU)] = {
1091 [C(L1D)] = {
1107 [C(L1I)] = {
1124 [C(LL)] = {
1149 [C(BPU)] = {
1284 [C(LL)] = {
1346 [C(LL)] = {
[all …]
/openbmc/linux/kernel/trace/
H A Dtrace_probe.h470 C(NO_REGULAR_FILE, "Not a regular file"), \
477 C(MAXACT_TOO_BIG, "Maxactive is too big"), \
492 C(BAD_STACK_NUM, "Invalid stack number"), \
495 C(BAD_REG_NAME, "Invalid register name"), \
497 C(BAD_IMM, "Invalid immediate value"), \
508 C(ARRAY_NO_CLOSE, "Array is not closed"), \
510 C(BAD_ARRAY_NUM, "Invalid array size"), \
512 C(BAD_TYPE, "Unknown type is specified"), \
515 C(BAD_BITFIELD, "Invalid bitfield"), \
547 #undef C
[all …]
/openbmc/linux/arch/x86/events/amd/
H A Dcore.c31 [ C(L1D) ] = {
45 [ C(L1I ) ] = {
59 [ C(LL ) ] = {
73 [ C(DTLB) ] = {
135 [C(L1D)] = {
149 [C(L1I)] = {
163 [C(LL)] = {
177 [C(DTLB)] = {
191 [C(ITLB)] = {
205 [C(BPU)] = {
[all …]
/openbmc/linux/lib/zstd/common/
H A Dcpu.h98 C(sse3, 0)
103 C(vmx, 5)
104 C(smx, 6)
105 C(eist, 7)
106 C(tm2, 8)
109 C(fma, 12)
114 C(dca, 18)
121 C(aes, 25)
124 C(avx, 28)
127 #undef C
[all …]
/openbmc/u-boot/lib/
H A Dsha1.c103 C = ctx->state[2]; in sha1_process()
110 P (A, B, C, D, E, W[0]); in sha1_process()
111 P (E, A, B, C, D, W[1]); in sha1_process()
112 P (D, E, A, B, C, W[2]); in sha1_process()
113 P (C, D, E, A, B, W[3]); in sha1_process()
114 P (B, C, D, E, A, W[4]); in sha1_process()
115 P (A, B, C, D, E, W[5]); in sha1_process()
116 P (E, A, B, C, D, W[6]); in sha1_process()
117 P (D, E, A, B, C, W[7]); in sha1_process()
118 P (C, D, E, A, B, W[8]); in sha1_process()
[all …]

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