Lines Matching refs:C
481 [ C(L1D ) ] = {
482 [ C(OP_READ) ] = {
483 [ C(RESULT_ACCESS) ] = 0x81d0,
484 [ C(RESULT_MISS) ] = 0xe124,
486 [ C(OP_WRITE) ] = {
487 [ C(RESULT_ACCESS) ] = 0x82d0,
490 [ C(L1I ) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_MISS) ] = 0xe424,
494 [ C(OP_WRITE) ] = {
495 [ C(RESULT_ACCESS) ] = -1,
496 [ C(RESULT_MISS) ] = -1,
499 [ C(LL ) ] = {
500 [ C(OP_READ) ] = {
501 [ C(RESULT_ACCESS) ] = 0x12a,
502 [ C(RESULT_MISS) ] = 0x12a,
504 [ C(OP_WRITE) ] = {
505 [ C(RESULT_ACCESS) ] = 0x12a,
506 [ C(RESULT_MISS) ] = 0x12a,
509 [ C(DTLB) ] = {
510 [ C(OP_READ) ] = {
511 [ C(RESULT_ACCESS) ] = 0x81d0,
512 [ C(RESULT_MISS) ] = 0xe12,
514 [ C(OP_WRITE) ] = {
515 [ C(RESULT_ACCESS) ] = 0x82d0,
516 [ C(RESULT_MISS) ] = 0xe13,
519 [ C(ITLB) ] = {
520 [ C(OP_READ) ] = {
521 [ C(RESULT_ACCESS) ] = -1,
522 [ C(RESULT_MISS) ] = 0xe11,
524 [ C(OP_WRITE) ] = {
525 [ C(RESULT_ACCESS) ] = -1,
526 [ C(RESULT_MISS) ] = -1,
528 [ C(OP_PREFETCH) ] = {
529 [ C(RESULT_ACCESS) ] = -1,
530 [ C(RESULT_MISS) ] = -1,
533 [ C(BPU ) ] = {
534 [ C(OP_READ) ] = {
535 [ C(RESULT_ACCESS) ] = 0x4c4,
536 [ C(RESULT_MISS) ] = 0x4c5,
538 [ C(OP_WRITE) ] = {
539 [ C(RESULT_ACCESS) ] = -1,
540 [ C(RESULT_MISS) ] = -1,
542 [ C(OP_PREFETCH) ] = {
543 [ C(RESULT_ACCESS) ] = -1,
544 [ C(RESULT_MISS) ] = -1,
547 [ C(NODE) ] = {
548 [ C(OP_READ) ] = {
549 [ C(RESULT_ACCESS) ] = 0x12a,
550 [ C(RESULT_MISS) ] = 0x12a,
560 [ C(LL ) ] = {
561 [ C(OP_READ) ] = {
562 [ C(RESULT_ACCESS) ] = 0x10001,
563 [ C(RESULT_MISS) ] = 0x3fbfc00001,
565 [ C(OP_WRITE) ] = {
566 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
567 [ C(RESULT_MISS) ] = 0x3f3fc00002,
570 [ C(NODE) ] = {
571 [ C(OP_READ) ] = {
572 [ C(RESULT_ACCESS) ] = 0x10c000001,
573 [ C(RESULT_MISS) ] = 0x3fb3000001,
627 [ C(L1D ) ] = {
628 [ C(OP_READ) ] = {
629 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
630 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
632 [ C(OP_WRITE) ] = {
633 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
634 [ C(RESULT_MISS) ] = 0x0,
636 [ C(OP_PREFETCH) ] = {
637 [ C(RESULT_ACCESS) ] = 0x0,
638 [ C(RESULT_MISS) ] = 0x0,
641 [ C(L1I ) ] = {
642 [ C(OP_READ) ] = {
643 [ C(RESULT_ACCESS) ] = 0x0,
644 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
646 [ C(OP_WRITE) ] = {
647 [ C(RESULT_ACCESS) ] = -1,
648 [ C(RESULT_MISS) ] = -1,
650 [ C(OP_PREFETCH) ] = {
651 [ C(RESULT_ACCESS) ] = 0x0,
652 [ C(RESULT_MISS) ] = 0x0,
655 [ C(LL ) ] = {
656 [ C(OP_READ) ] = {
657 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
658 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
660 [ C(OP_WRITE) ] = {
661 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
662 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
664 [ C(OP_PREFETCH) ] = {
665 [ C(RESULT_ACCESS) ] = 0x0,
666 [ C(RESULT_MISS) ] = 0x0,
669 [ C(DTLB) ] = {
670 [ C(OP_READ) ] = {
671 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
672 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
674 [ C(OP_WRITE) ] = {
675 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
676 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
678 [ C(OP_PREFETCH) ] = {
679 [ C(RESULT_ACCESS) ] = 0x0,
680 [ C(RESULT_MISS) ] = 0x0,
683 [ C(ITLB) ] = {
684 [ C(OP_READ) ] = {
685 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
686 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
688 [ C(OP_WRITE) ] = {
689 [ C(RESULT_ACCESS) ] = -1,
690 [ C(RESULT_MISS) ] = -1,
692 [ C(OP_PREFETCH) ] = {
693 [ C(RESULT_ACCESS) ] = -1,
694 [ C(RESULT_MISS) ] = -1,
697 [ C(BPU ) ] = {
698 [ C(OP_READ) ] = {
699 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
700 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
702 [ C(OP_WRITE) ] = {
703 [ C(RESULT_ACCESS) ] = -1,
704 [ C(RESULT_MISS) ] = -1,
706 [ C(OP_PREFETCH) ] = {
707 [ C(RESULT_ACCESS) ] = -1,
708 [ C(RESULT_MISS) ] = -1,
711 [ C(NODE) ] = {
712 [ C(OP_READ) ] = {
713 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
714 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
716 [ C(OP_WRITE) ] = {
717 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
718 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
720 [ C(OP_PREFETCH) ] = {
721 [ C(RESULT_ACCESS) ] = 0x0,
722 [ C(RESULT_MISS) ] = 0x0,
732 [ C(LL ) ] = {
733 [ C(OP_READ) ] = {
734 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
736 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
740 [ C(OP_WRITE) ] = {
741 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
743 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
747 [ C(OP_PREFETCH) ] = {
748 [ C(RESULT_ACCESS) ] = 0x0,
749 [ C(RESULT_MISS) ] = 0x0,
752 [ C(NODE) ] = {
753 [ C(OP_READ) ] = {
754 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
756 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
759 [ C(OP_WRITE) ] = {
760 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
762 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
765 [ C(OP_PREFETCH) ] = {
766 [ C(RESULT_ACCESS) ] = 0x0,
767 [ C(RESULT_MISS) ] = 0x0,
820 [ C(LL ) ] = {
821 [ C(OP_READ) ] = {
822 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
823 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
825 [ C(OP_WRITE) ] = {
826 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
827 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
829 [ C(OP_PREFETCH) ] = {
830 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
831 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
834 [ C(NODE) ] = {
835 [ C(OP_READ) ] = {
836 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
837 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
839 [ C(OP_WRITE) ] = {
840 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
841 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
843 [ C(OP_PREFETCH) ] = {
844 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
845 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
855 [ C(L1D) ] = {
856 [ C(OP_READ) ] = {
857 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
858 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
860 [ C(OP_WRITE) ] = {
861 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
862 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
864 [ C(OP_PREFETCH) ] = {
865 [ C(RESULT_ACCESS) ] = 0x0,
866 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
869 [ C(L1I ) ] = {
870 [ C(OP_READ) ] = {
871 [ C(RESULT_ACCESS) ] = 0x0,
872 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
874 [ C(OP_WRITE) ] = {
875 [ C(RESULT_ACCESS) ] = -1,
876 [ C(RESULT_MISS) ] = -1,
878 [ C(OP_PREFETCH) ] = {
879 [ C(RESULT_ACCESS) ] = 0x0,
880 [ C(RESULT_MISS) ] = 0x0,
883 [ C(LL ) ] = {
884 [ C(OP_READ) ] = {
886 [ C(RESULT_ACCESS) ] = 0x01b7,
888 [ C(RESULT_MISS) ] = 0x01b7,
890 [ C(OP_WRITE) ] = {
892 [ C(RESULT_ACCESS) ] = 0x01b7,
894 [ C(RESULT_MISS) ] = 0x01b7,
896 [ C(OP_PREFETCH) ] = {
898 [ C(RESULT_ACCESS) ] = 0x01b7,
900 [ C(RESULT_MISS) ] = 0x01b7,
903 [ C(DTLB) ] = {
904 [ C(OP_READ) ] = {
905 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
906 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
908 [ C(OP_WRITE) ] = {
909 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
910 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
912 [ C(OP_PREFETCH) ] = {
913 [ C(RESULT_ACCESS) ] = 0x0,
914 [ C(RESULT_MISS) ] = 0x0,
917 [ C(ITLB) ] = {
918 [ C(OP_READ) ] = {
919 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
920 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
922 [ C(OP_WRITE) ] = {
923 [ C(RESULT_ACCESS) ] = -1,
924 [ C(RESULT_MISS) ] = -1,
926 [ C(OP_PREFETCH) ] = {
927 [ C(RESULT_ACCESS) ] = -1,
928 [ C(RESULT_MISS) ] = -1,
931 [ C(BPU ) ] = {
932 [ C(OP_READ) ] = {
933 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
934 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
936 [ C(OP_WRITE) ] = {
937 [ C(RESULT_ACCESS) ] = -1,
938 [ C(RESULT_MISS) ] = -1,
940 [ C(OP_PREFETCH) ] = {
941 [ C(RESULT_ACCESS) ] = -1,
942 [ C(RESULT_MISS) ] = -1,
945 [ C(NODE) ] = {
946 [ C(OP_READ) ] = {
947 [ C(RESULT_ACCESS) ] = 0x01b7,
948 [ C(RESULT_MISS) ] = 0x01b7,
950 [ C(OP_WRITE) ] = {
951 [ C(RESULT_ACCESS) ] = 0x01b7,
952 [ C(RESULT_MISS) ] = 0x01b7,
954 [ C(OP_PREFETCH) ] = {
955 [ C(RESULT_ACCESS) ] = 0x01b7,
956 [ C(RESULT_MISS) ] = 0x01b7,
1011 [ C(L1D ) ] = {
1012 [ C(OP_READ) ] = {
1013 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1014 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1016 [ C(OP_WRITE) ] = {
1017 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1018 [ C(RESULT_MISS) ] = 0x0,
1020 [ C(OP_PREFETCH) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x0,
1022 [ C(RESULT_MISS) ] = 0x0,
1025 [ C(L1I ) ] = {
1026 [ C(OP_READ) ] = {
1027 [ C(RESULT_ACCESS) ] = 0x0,
1028 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1030 [ C(OP_WRITE) ] = {
1031 [ C(RESULT_ACCESS) ] = -1,
1032 [ C(RESULT_MISS) ] = -1,
1034 [ C(OP_PREFETCH) ] = {
1035 [ C(RESULT_ACCESS) ] = 0x0,
1036 [ C(RESULT_MISS) ] = 0x0,
1039 [ C(LL ) ] = {
1040 [ C(OP_READ) ] = {
1041 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1042 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1044 [ C(OP_WRITE) ] = {
1045 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1046 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1048 [ C(OP_PREFETCH) ] = {
1049 [ C(RESULT_ACCESS) ] = 0x0,
1050 [ C(RESULT_MISS) ] = 0x0,
1053 [ C(DTLB) ] = {
1054 [ C(OP_READ) ] = {
1055 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1056 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1058 [ C(OP_WRITE) ] = {
1059 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1060 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1062 [ C(OP_PREFETCH) ] = {
1063 [ C(RESULT_ACCESS) ] = 0x0,
1064 [ C(RESULT_MISS) ] = 0x0,
1067 [ C(ITLB) ] = {
1068 [ C(OP_READ) ] = {
1069 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1070 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1072 [ C(OP_WRITE) ] = {
1073 [ C(RESULT_ACCESS) ] = -1,
1074 [ C(RESULT_MISS) ] = -1,
1076 [ C(OP_PREFETCH) ] = {
1077 [ C(RESULT_ACCESS) ] = -1,
1078 [ C(RESULT_MISS) ] = -1,
1081 [ C(BPU ) ] = {
1082 [ C(OP_READ) ] = {
1083 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1084 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1086 [ C(OP_WRITE) ] = {
1087 [ C(RESULT_ACCESS) ] = -1,
1088 [ C(RESULT_MISS) ] = -1,
1090 [ C(OP_PREFETCH) ] = {
1091 [ C(RESULT_ACCESS) ] = -1,
1092 [ C(RESULT_MISS) ] = -1,
1095 [ C(NODE) ] = {
1096 [ C(OP_READ) ] = {
1097 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1098 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1100 [ C(OP_WRITE) ] = {
1101 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1102 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1104 [ C(OP_PREFETCH) ] = {
1105 [ C(RESULT_ACCESS) ] = 0x0,
1106 [ C(RESULT_MISS) ] = 0x0,
1116 [ C(LL ) ] = {
1117 [ C(OP_READ) ] = {
1118 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1120 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1123 [ C(OP_WRITE) ] = {
1124 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1126 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1129 [ C(OP_PREFETCH) ] = {
1130 [ C(RESULT_ACCESS) ] = 0x0,
1131 [ C(RESULT_MISS) ] = 0x0,
1134 [ C(NODE) ] = {
1135 [ C(OP_READ) ] = {
1136 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1139 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1143 [ C(OP_WRITE) ] = {
1144 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1147 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1151 [ C(OP_PREFETCH) ] = {
1152 [ C(RESULT_ACCESS) ] = 0x0,
1153 [ C(RESULT_MISS) ] = 0x0,
1163 [ C(L1D) ] = {
1164 [ C(OP_READ) ] = {
1165 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1166 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1168 [ C(OP_WRITE) ] = {
1169 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1170 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1172 [ C(OP_PREFETCH) ] = {
1173 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1174 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1177 [ C(L1I ) ] = {
1178 [ C(OP_READ) ] = {
1179 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1180 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1182 [ C(OP_WRITE) ] = {
1183 [ C(RESULT_ACCESS) ] = -1,
1184 [ C(RESULT_MISS) ] = -1,
1186 [ C(OP_PREFETCH) ] = {
1187 [ C(RESULT_ACCESS) ] = 0x0,
1188 [ C(RESULT_MISS) ] = 0x0,
1191 [ C(LL ) ] = {
1192 [ C(OP_READ) ] = {
1194 [ C(RESULT_ACCESS) ] = 0x01b7,
1196 [ C(RESULT_MISS) ] = 0x01b7,
1202 [ C(OP_WRITE) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x01b7,
1206 [ C(RESULT_MISS) ] = 0x01b7,
1208 [ C(OP_PREFETCH) ] = {
1210 [ C(RESULT_ACCESS) ] = 0x01b7,
1212 [ C(RESULT_MISS) ] = 0x01b7,
1215 [ C(DTLB) ] = {
1216 [ C(OP_READ) ] = {
1217 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1218 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1220 [ C(OP_WRITE) ] = {
1221 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1222 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1224 [ C(OP_PREFETCH) ] = {
1225 [ C(RESULT_ACCESS) ] = 0x0,
1226 [ C(RESULT_MISS) ] = 0x0,
1229 [ C(ITLB) ] = {
1230 [ C(OP_READ) ] = {
1231 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1232 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1234 [ C(OP_WRITE) ] = {
1235 [ C(RESULT_ACCESS) ] = -1,
1236 [ C(RESULT_MISS) ] = -1,
1238 [ C(OP_PREFETCH) ] = {
1239 [ C(RESULT_ACCESS) ] = -1,
1240 [ C(RESULT_MISS) ] = -1,
1243 [ C(BPU ) ] = {
1244 [ C(OP_READ) ] = {
1245 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1246 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1248 [ C(OP_WRITE) ] = {
1249 [ C(RESULT_ACCESS) ] = -1,
1250 [ C(RESULT_MISS) ] = -1,
1252 [ C(OP_PREFETCH) ] = {
1253 [ C(RESULT_ACCESS) ] = -1,
1254 [ C(RESULT_MISS) ] = -1,
1257 [ C(NODE) ] = {
1258 [ C(OP_READ) ] = {
1259 [ C(RESULT_ACCESS) ] = 0x01b7,
1260 [ C(RESULT_MISS) ] = 0x01b7,
1262 [ C(OP_WRITE) ] = {
1263 [ C(RESULT_ACCESS) ] = 0x01b7,
1264 [ C(RESULT_MISS) ] = 0x01b7,
1266 [ C(OP_PREFETCH) ] = {
1267 [ C(RESULT_ACCESS) ] = 0x01b7,
1268 [ C(RESULT_MISS) ] = 0x01b7,
1311 [ C(LL ) ] = {
1312 [ C(OP_READ) ] = {
1313 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1314 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1316 [ C(OP_WRITE) ] = {
1317 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1318 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1320 [ C(OP_PREFETCH) ] = {
1321 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1322 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1325 [ C(NODE) ] = {
1326 [ C(OP_READ) ] = {
1327 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1328 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1330 [ C(OP_WRITE) ] = {
1331 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1332 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1334 [ C(OP_PREFETCH) ] = {
1335 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1336 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1346 [ C(L1D) ] = {
1347 [ C(OP_READ) ] = {
1348 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1349 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1351 [ C(OP_WRITE) ] = {
1352 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1353 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1355 [ C(OP_PREFETCH) ] = {
1356 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1357 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1360 [ C(L1I ) ] = {
1361 [ C(OP_READ) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1363 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1365 [ C(OP_WRITE) ] = {
1366 [ C(RESULT_ACCESS) ] = -1,
1367 [ C(RESULT_MISS) ] = -1,
1369 [ C(OP_PREFETCH) ] = {
1370 [ C(RESULT_ACCESS) ] = 0x0,
1371 [ C(RESULT_MISS) ] = 0x0,
1374 [ C(LL ) ] = {
1375 [ C(OP_READ) ] = {
1377 [ C(RESULT_ACCESS) ] = 0x01b7,
1379 [ C(RESULT_MISS) ] = 0x01b7,
1385 [ C(OP_WRITE) ] = {
1387 [ C(RESULT_ACCESS) ] = 0x01b7,
1389 [ C(RESULT_MISS) ] = 0x01b7,
1391 [ C(OP_PREFETCH) ] = {
1393 [ C(RESULT_ACCESS) ] = 0x01b7,
1395 [ C(RESULT_MISS) ] = 0x01b7,
1398 [ C(DTLB) ] = {
1399 [ C(OP_READ) ] = {
1400 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1401 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1403 [ C(OP_WRITE) ] = {
1404 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1405 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1407 [ C(OP_PREFETCH) ] = {
1408 [ C(RESULT_ACCESS) ] = 0x0,
1409 [ C(RESULT_MISS) ] = 0x0,
1412 [ C(ITLB) ] = {
1413 [ C(OP_READ) ] = {
1414 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1415 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1417 [ C(OP_WRITE) ] = {
1418 [ C(RESULT_ACCESS) ] = -1,
1419 [ C(RESULT_MISS) ] = -1,
1421 [ C(OP_PREFETCH) ] = {
1422 [ C(RESULT_ACCESS) ] = -1,
1423 [ C(RESULT_MISS) ] = -1,
1426 [ C(BPU ) ] = {
1427 [ C(OP_READ) ] = {
1428 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1429 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1431 [ C(OP_WRITE) ] = {
1432 [ C(RESULT_ACCESS) ] = -1,
1433 [ C(RESULT_MISS) ] = -1,
1435 [ C(OP_PREFETCH) ] = {
1436 [ C(RESULT_ACCESS) ] = -1,
1437 [ C(RESULT_MISS) ] = -1,
1440 [ C(NODE) ] = {
1441 [ C(OP_READ) ] = {
1442 [ C(RESULT_ACCESS) ] = 0x01b7,
1443 [ C(RESULT_MISS) ] = 0x01b7,
1445 [ C(OP_WRITE) ] = {
1446 [ C(RESULT_ACCESS) ] = 0x01b7,
1447 [ C(RESULT_MISS) ] = 0x01b7,
1449 [ C(OP_PREFETCH) ] = {
1450 [ C(RESULT_ACCESS) ] = 0x01b7,
1451 [ C(RESULT_MISS) ] = 0x01b7,
1461 [ C(L1D) ] = {
1462 [ C(OP_READ) ] = {
1463 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1464 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1466 [ C(OP_WRITE) ] = {
1467 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1468 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1470 [ C(OP_PREFETCH) ] = {
1471 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1472 [ C(RESULT_MISS) ] = 0,
1475 [ C(L1I ) ] = {
1476 [ C(OP_READ) ] = {
1477 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1478 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1480 [ C(OP_WRITE) ] = {
1481 [ C(RESULT_ACCESS) ] = -1,
1482 [ C(RESULT_MISS) ] = -1,
1484 [ C(OP_PREFETCH) ] = {
1485 [ C(RESULT_ACCESS) ] = 0,
1486 [ C(RESULT_MISS) ] = 0,
1489 [ C(LL ) ] = {
1490 [ C(OP_READ) ] = {
1491 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1492 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1494 [ C(OP_WRITE) ] = {
1495 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1496 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1498 [ C(OP_PREFETCH) ] = {
1499 [ C(RESULT_ACCESS) ] = 0,
1500 [ C(RESULT_MISS) ] = 0,
1503 [ C(DTLB) ] = {
1504 [ C(OP_READ) ] = {
1505 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1506 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1508 [ C(OP_WRITE) ] = {
1509 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1510 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1512 [ C(OP_PREFETCH) ] = {
1513 [ C(RESULT_ACCESS) ] = 0,
1514 [ C(RESULT_MISS) ] = 0,
1517 [ C(ITLB) ] = {
1518 [ C(OP_READ) ] = {
1519 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1520 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1522 [ C(OP_WRITE) ] = {
1523 [ C(RESULT_ACCESS) ] = -1,
1524 [ C(RESULT_MISS) ] = -1,
1526 [ C(OP_PREFETCH) ] = {
1527 [ C(RESULT_ACCESS) ] = -1,
1528 [ C(RESULT_MISS) ] = -1,
1531 [ C(BPU ) ] = {
1532 [ C(OP_READ) ] = {
1533 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1534 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1536 [ C(OP_WRITE) ] = {
1537 [ C(RESULT_ACCESS) ] = -1,
1538 [ C(RESULT_MISS) ] = -1,
1540 [ C(OP_PREFETCH) ] = {
1541 [ C(RESULT_ACCESS) ] = -1,
1542 [ C(RESULT_MISS) ] = -1,
1552 [ C(L1D) ] = {
1553 [ C(OP_READ) ] = {
1554 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1555 [ C(RESULT_MISS) ] = 0,
1557 [ C(OP_WRITE) ] = {
1558 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1559 [ C(RESULT_MISS) ] = 0,
1561 [ C(OP_PREFETCH) ] = {
1562 [ C(RESULT_ACCESS) ] = 0x0,
1563 [ C(RESULT_MISS) ] = 0,
1566 [ C(L1I ) ] = {
1567 [ C(OP_READ) ] = {
1568 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1569 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1571 [ C(OP_WRITE) ] = {
1572 [ C(RESULT_ACCESS) ] = -1,
1573 [ C(RESULT_MISS) ] = -1,
1575 [ C(OP_PREFETCH) ] = {
1576 [ C(RESULT_ACCESS) ] = 0,
1577 [ C(RESULT_MISS) ] = 0,
1580 [ C(LL ) ] = {
1581 [ C(OP_READ) ] = {
1582 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1583 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1585 [ C(OP_WRITE) ] = {
1586 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1587 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1589 [ C(OP_PREFETCH) ] = {
1590 [ C(RESULT_ACCESS) ] = 0,
1591 [ C(RESULT_MISS) ] = 0,
1594 [ C(DTLB) ] = {
1595 [ C(OP_READ) ] = {
1596 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1597 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1599 [ C(OP_WRITE) ] = {
1600 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1601 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1603 [ C(OP_PREFETCH) ] = {
1604 [ C(RESULT_ACCESS) ] = 0,
1605 [ C(RESULT_MISS) ] = 0,
1608 [ C(ITLB) ] = {
1609 [ C(OP_READ) ] = {
1610 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1611 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1613 [ C(OP_WRITE) ] = {
1614 [ C(RESULT_ACCESS) ] = -1,
1615 [ C(RESULT_MISS) ] = -1,
1617 [ C(OP_PREFETCH) ] = {
1618 [ C(RESULT_ACCESS) ] = -1,
1619 [ C(RESULT_MISS) ] = -1,
1622 [ C(BPU ) ] = {
1623 [ C(OP_READ) ] = {
1624 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1625 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1627 [ C(OP_WRITE) ] = {
1628 [ C(RESULT_ACCESS) ] = -1,
1629 [ C(RESULT_MISS) ] = -1,
1631 [ C(OP_PREFETCH) ] = {
1632 [ C(RESULT_ACCESS) ] = -1,
1633 [ C(RESULT_MISS) ] = -1,
1682 [ C(LL ) ] = {
1683 [ C(OP_READ) ] = {
1684 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1685 [ C(RESULT_MISS) ] = 0,
1687 [ C(OP_WRITE) ] = {
1688 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1689 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1691 [ C(OP_PREFETCH) ] = {
1692 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1693 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1703 [ C(L1D) ] = {
1704 [ C(OP_READ) ] = {
1705 [ C(RESULT_ACCESS) ] = 0,
1706 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1708 [ C(OP_WRITE) ] = {
1709 [ C(RESULT_ACCESS) ] = 0,
1710 [ C(RESULT_MISS) ] = 0,
1712 [ C(OP_PREFETCH) ] = {
1713 [ C(RESULT_ACCESS) ] = 0,
1714 [ C(RESULT_MISS) ] = 0,
1717 [ C(L1I ) ] = {
1718 [ C(OP_READ) ] = {
1719 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1720 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1722 [ C(OP_WRITE) ] = {
1723 [ C(RESULT_ACCESS) ] = -1,
1724 [ C(RESULT_MISS) ] = -1,
1726 [ C(OP_PREFETCH) ] = {
1727 [ C(RESULT_ACCESS) ] = 0,
1728 [ C(RESULT_MISS) ] = 0,
1731 [ C(LL ) ] = {
1732 [ C(OP_READ) ] = {
1734 [ C(RESULT_ACCESS) ] = 0x01b7,
1735 [ C(RESULT_MISS) ] = 0,
1737 [ C(OP_WRITE) ] = {
1739 [ C(RESULT_ACCESS) ] = 0x01b7,
1741 [ C(RESULT_MISS) ] = 0x01b7,
1743 [ C(OP_PREFETCH) ] = {
1745 [ C(RESULT_ACCESS) ] = 0x01b7,
1747 [ C(RESULT_MISS) ] = 0x01b7,
1750 [ C(DTLB) ] = {
1751 [ C(OP_READ) ] = {
1752 [ C(RESULT_ACCESS) ] = 0,
1753 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1755 [ C(OP_WRITE) ] = {
1756 [ C(RESULT_ACCESS) ] = 0,
1757 [ C(RESULT_MISS) ] = 0,
1759 [ C(OP_PREFETCH) ] = {
1760 [ C(RESULT_ACCESS) ] = 0,
1761 [ C(RESULT_MISS) ] = 0,
1764 [ C(ITLB) ] = {
1765 [ C(OP_READ) ] = {
1766 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1767 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1769 [ C(OP_WRITE) ] = {
1770 [ C(RESULT_ACCESS) ] = -1,
1771 [ C(RESULT_MISS) ] = -1,
1773 [ C(OP_PREFETCH) ] = {
1774 [ C(RESULT_ACCESS) ] = -1,
1775 [ C(RESULT_MISS) ] = -1,
1778 [ C(BPU ) ] = {
1779 [ C(OP_READ) ] = {
1780 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1781 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1783 [ C(OP_WRITE) ] = {
1784 [ C(RESULT_ACCESS) ] = -1,
1785 [ C(RESULT_MISS) ] = -1,
1787 [ C(OP_PREFETCH) ] = {
1788 [ C(RESULT_ACCESS) ] = -1,
1789 [ C(RESULT_MISS) ] = -1,
1837 [C(L1D)] = {
1838 [C(OP_READ)] = {
1839 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1840 [C(RESULT_MISS)] = 0x0,
1842 [C(OP_WRITE)] = {
1843 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1844 [C(RESULT_MISS)] = 0x0,
1846 [C(OP_PREFETCH)] = {
1847 [C(RESULT_ACCESS)] = 0x0,
1848 [C(RESULT_MISS)] = 0x0,
1851 [C(L1I)] = {
1852 [C(OP_READ)] = {
1853 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1854 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1856 [C(OP_WRITE)] = {
1857 [C(RESULT_ACCESS)] = -1,
1858 [C(RESULT_MISS)] = -1,
1860 [C(OP_PREFETCH)] = {
1861 [C(RESULT_ACCESS)] = 0x0,
1862 [C(RESULT_MISS)] = 0x0,
1865 [C(LL)] = {
1866 [C(OP_READ)] = {
1867 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1868 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1870 [C(OP_WRITE)] = {
1871 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1872 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1874 [C(OP_PREFETCH)] = {
1875 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1876 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1879 [C(DTLB)] = {
1880 [C(OP_READ)] = {
1881 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1882 [C(RESULT_MISS)] = 0x0,
1884 [C(OP_WRITE)] = {
1885 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1886 [C(RESULT_MISS)] = 0x0,
1888 [C(OP_PREFETCH)] = {
1889 [C(RESULT_ACCESS)] = 0x0,
1890 [C(RESULT_MISS)] = 0x0,
1893 [C(ITLB)] = {
1894 [C(OP_READ)] = {
1895 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1896 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1898 [C(OP_WRITE)] = {
1899 [C(RESULT_ACCESS)] = -1,
1900 [C(RESULT_MISS)] = -1,
1902 [C(OP_PREFETCH)] = {
1903 [C(RESULT_ACCESS)] = -1,
1904 [C(RESULT_MISS)] = -1,
1907 [C(BPU)] = {
1908 [C(OP_READ)] = {
1909 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1910 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1912 [C(OP_WRITE)] = {
1913 [C(RESULT_ACCESS)] = -1,
1914 [C(RESULT_MISS)] = -1,
1916 [C(OP_PREFETCH)] = {
1917 [C(RESULT_ACCESS)] = -1,
1918 [C(RESULT_MISS)] = -1,
1927 [C(LL)] = {
1928 [C(OP_READ)] = {
1929 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1931 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1934 [C(OP_WRITE)] = {
1935 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1937 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1940 [C(OP_PREFETCH)] = {
1941 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1943 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1953 [C(L1D)] = {
1954 [C(OP_READ)] = {
1955 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1956 [C(RESULT_MISS)] = 0x0,
1958 [C(OP_WRITE)] = {
1959 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1960 [C(RESULT_MISS)] = 0x0,
1962 [C(OP_PREFETCH)] = {
1963 [C(RESULT_ACCESS)] = 0x0,
1964 [C(RESULT_MISS)] = 0x0,
1967 [C(L1I)] = {
1968 [C(OP_READ)] = {
1969 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1970 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1972 [C(OP_WRITE)] = {
1973 [C(RESULT_ACCESS)] = -1,
1974 [C(RESULT_MISS)] = -1,
1976 [C(OP_PREFETCH)] = {
1977 [C(RESULT_ACCESS)] = 0x0,
1978 [C(RESULT_MISS)] = 0x0,
1981 [C(LL)] = {
1982 [C(OP_READ)] = {
1983 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1984 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1986 [C(OP_WRITE)] = {
1987 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1988 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1990 [C(OP_PREFETCH)] = {
1991 [C(RESULT_ACCESS)] = 0x0,
1992 [C(RESULT_MISS)] = 0x0,
1995 [C(DTLB)] = {
1996 [C(OP_READ)] = {
1997 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1998 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2000 [C(OP_WRITE)] = {
2001 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2002 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2004 [C(OP_PREFETCH)] = {
2005 [C(RESULT_ACCESS)] = 0x0,
2006 [C(RESULT_MISS)] = 0x0,
2009 [C(ITLB)] = {
2010 [C(OP_READ)] = {
2011 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2012 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2014 [C(OP_WRITE)] = {
2015 [C(RESULT_ACCESS)] = -1,
2016 [C(RESULT_MISS)] = -1,
2018 [C(OP_PREFETCH)] = {
2019 [C(RESULT_ACCESS)] = -1,
2020 [C(RESULT_MISS)] = -1,
2023 [C(BPU)] = {
2024 [C(OP_READ)] = {
2025 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2026 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2028 [C(OP_WRITE)] = {
2029 [C(RESULT_ACCESS)] = -1,
2030 [C(RESULT_MISS)] = -1,
2032 [C(OP_PREFETCH)] = {
2033 [C(RESULT_ACCESS)] = -1,
2034 [C(RESULT_MISS)] = -1,
2043 [C(LL)] = {
2044 [C(OP_READ)] = {
2045 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2047 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2050 [C(OP_WRITE)] = {
2051 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2053 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2056 [C(OP_PREFETCH)] = {
2057 [C(RESULT_ACCESS)] = 0x0,
2058 [C(RESULT_MISS)] = 0x0,
2075 [C(LL)] = {
2076 [C(OP_READ)] = {
2077 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2079 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2082 [C(OP_WRITE)] = {
2083 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2085 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2088 [C(OP_PREFETCH)] = {
2089 [C(RESULT_ACCESS)] = 0x0,
2090 [C(RESULT_MISS)] = 0x0,
2173 [C(LL)] = {
2174 [C(OP_READ)] = {
2175 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2176 [C(RESULT_MISS)] = 0,
2178 [C(OP_WRITE)] = {
2179 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2180 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2182 [C(OP_PREFETCH)] = {
2183 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2184 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
6198 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6225 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6256 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6357 …hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MI… in intel_pmu_init()
6434 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
6436 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
6438 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
6440 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()
6556 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6741 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()