1f4344b19SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
28c002dbdSMadhavan Srinivasan /*
38c002dbdSMadhavan Srinivasan * Performance counter support for POWER9 processors.
48c002dbdSMadhavan Srinivasan *
58c002dbdSMadhavan Srinivasan * Copyright 2009 Paul Mackerras, IBM Corporation.
68c002dbdSMadhavan Srinivasan * Copyright 2013 Michael Ellerman, IBM Corporation.
78c002dbdSMadhavan Srinivasan * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
88c002dbdSMadhavan Srinivasan */
98c002dbdSMadhavan Srinivasan
108c002dbdSMadhavan Srinivasan #define pr_fmt(fmt) "power9-pmu: " fmt
118c002dbdSMadhavan Srinivasan
128c002dbdSMadhavan Srinivasan #include "isa207-common.h"
138c002dbdSMadhavan Srinivasan
148c002dbdSMadhavan Srinivasan /*
1518201b20SMadhavan Srinivasan * Raw event encoding for Power9:
1618201b20SMadhavan Srinivasan *
1718201b20SMadhavan Srinivasan * 60 56 52 48 44 40 36 32
1818201b20SMadhavan Srinivasan * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
1918201b20SMadhavan Srinivasan * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ]
2018201b20SMadhavan Srinivasan * | | | | |
2178a16d9fSMadhavan Srinivasan * | | *- IFM (Linux) | thresh start/stop -*
2218201b20SMadhavan Srinivasan * | *- BHRB (Linux) *sm
2318201b20SMadhavan Srinivasan * *- EBB (Linux)
2418201b20SMadhavan Srinivasan *
2518201b20SMadhavan Srinivasan * 28 24 20 16 12 8 4 0
2618201b20SMadhavan Srinivasan * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
2718201b20SMadhavan Srinivasan * [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ]
2818201b20SMadhavan Srinivasan * | | | | |
2918201b20SMadhavan Srinivasan * | | | | *- mark
3018201b20SMadhavan Srinivasan * | | *- L1/L2/L3 cache_sel |
3118201b20SMadhavan Srinivasan * | | |
3218201b20SMadhavan Srinivasan * | *- sampling mode for marked events *- combine
3318201b20SMadhavan Srinivasan * |
3418201b20SMadhavan Srinivasan * *- thresh_sel
3518201b20SMadhavan Srinivasan *
3618201b20SMadhavan Srinivasan * Below uses IBM bit numbering.
3718201b20SMadhavan Srinivasan *
3818201b20SMadhavan Srinivasan * MMCR1[x:y] = unit (PMCxUNIT)
3918201b20SMadhavan Srinivasan * MMCR1[24] = pmc1combine[0]
4018201b20SMadhavan Srinivasan * MMCR1[25] = pmc1combine[1]
4118201b20SMadhavan Srinivasan * MMCR1[26] = pmc2combine[0]
4218201b20SMadhavan Srinivasan * MMCR1[27] = pmc2combine[1]
4318201b20SMadhavan Srinivasan * MMCR1[28] = pmc3combine[0]
4418201b20SMadhavan Srinivasan * MMCR1[29] = pmc3combine[1]
4518201b20SMadhavan Srinivasan * MMCR1[30] = pmc4combine[0]
4618201b20SMadhavan Srinivasan * MMCR1[31] = pmc4combine[1]
4718201b20SMadhavan Srinivasan *
4818201b20SMadhavan Srinivasan * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
4978a16d9fSMadhavan Srinivasan * MMCR1[20:27] = thresh_ctl
5018201b20SMadhavan Srinivasan * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
5178a16d9fSMadhavan Srinivasan * MMCR1[20:27] = thresh_ctl
5218201b20SMadhavan Srinivasan * else
5318201b20SMadhavan Srinivasan * MMCRA[48:55] = thresh_ctl (THRESH START/END)
5418201b20SMadhavan Srinivasan *
5518201b20SMadhavan Srinivasan * if thresh_sel:
5618201b20SMadhavan Srinivasan * MMCRA[45:47] = thresh_sel
5718201b20SMadhavan Srinivasan *
5818201b20SMadhavan Srinivasan * if thresh_cmp:
5918201b20SMadhavan Srinivasan * MMCRA[9:11] = thresh_cmp[0:2]
6018201b20SMadhavan Srinivasan * MMCRA[12:18] = thresh_cmp[3:9]
6118201b20SMadhavan Srinivasan *
6218201b20SMadhavan Srinivasan * MMCR1[16] = cache_sel[2]
6318201b20SMadhavan Srinivasan * MMCR1[17] = cache_sel[3]
6418201b20SMadhavan Srinivasan *
6518201b20SMadhavan Srinivasan * if mark:
6618201b20SMadhavan Srinivasan * MMCRA[63] = 1 (SAMPLE_ENABLE)
6718201b20SMadhavan Srinivasan * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
6818201b20SMadhavan Srinivasan * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
6918201b20SMadhavan Srinivasan *
7018201b20SMadhavan Srinivasan * if EBB and BHRB:
7118201b20SMadhavan Srinivasan * MMCRA[32:33] = IFM
7218201b20SMadhavan Srinivasan *
7318201b20SMadhavan Srinivasan * MMCRA[SDAR_MODE] = sm
7418201b20SMadhavan Srinivasan */
7518201b20SMadhavan Srinivasan
7618201b20SMadhavan Srinivasan /*
778c002dbdSMadhavan Srinivasan * Some power9 event codes.
788c002dbdSMadhavan Srinivasan */
798c002dbdSMadhavan Srinivasan #define EVENT(_name, _code) _name = _code,
808c002dbdSMadhavan Srinivasan
818c002dbdSMadhavan Srinivasan enum {
828c002dbdSMadhavan Srinivasan #include "power9-events-list.h"
838c002dbdSMadhavan Srinivasan };
848c002dbdSMadhavan Srinivasan
858c002dbdSMadhavan Srinivasan #undef EVENT
868c002dbdSMadhavan Srinivasan
878c002dbdSMadhavan Srinivasan /* MMCRA IFM bits - POWER9 */
888c002dbdSMadhavan Srinivasan #define POWER9_MMCRA_IFM1 0x0000000040000000UL
898c002dbdSMadhavan Srinivasan #define POWER9_MMCRA_IFM2 0x0000000080000000UL
908c002dbdSMadhavan Srinivasan #define POWER9_MMCRA_IFM3 0x00000000C0000000UL
913202e35eSRavi Bangoria #define POWER9_MMCRA_BHRB_MASK 0x00000000C0000000UL
928c002dbdSMadhavan Srinivasan
93781fa481SAnju T Sudhakar extern u64 PERF_REG_EXTENDED_MASK;
94781fa481SAnju T Sudhakar
9564acab4eSMadhavan Srinivasan /* Nasty Power9 specific hack */
9664acab4eSMadhavan Srinivasan #define PVR_POWER9_CUMULUS 0x00002000
9764acab4eSMadhavan Srinivasan
9860b00025SMadhavan Srinivasan /* PowerISA v2.07 format attribute structure*/
996b3a3e12SRohan McLure extern const struct attribute_group isa207_pmu_format_group;
10060b00025SMadhavan Srinivasan
101cacaeb0cSWang Wensheng static int p9_dd21_bl_ev[] = {
10264acab4eSMadhavan Srinivasan PM_MRK_ST_DONE_L2,
10364acab4eSMadhavan Srinivasan PM_RADIX_PWC_L1_HIT,
10464acab4eSMadhavan Srinivasan PM_FLOP_CMPL,
10564acab4eSMadhavan Srinivasan PM_MRK_NTF_FIN,
10664acab4eSMadhavan Srinivasan PM_RADIX_PWC_L2_HIT,
10764acab4eSMadhavan Srinivasan PM_IFETCH_THROTTLE,
10864acab4eSMadhavan Srinivasan PM_MRK_L2_TM_ST_ABORT_SISTER,
10964acab4eSMadhavan Srinivasan PM_RADIX_PWC_L3_HIT,
11064acab4eSMadhavan Srinivasan PM_RUN_CYC_SMT2_MODE,
11164acab4eSMadhavan Srinivasan PM_TM_TX_PASS_RUN_INST,
11264acab4eSMadhavan Srinivasan PM_DISP_HELD_SYNC_HOLD,
11364acab4eSMadhavan Srinivasan };
11464acab4eSMadhavan Srinivasan
115cacaeb0cSWang Wensheng static int p9_dd22_bl_ev[] = {
116ac96588dSMadhavan Srinivasan PM_DTLB_MISS_16G,
117ac96588dSMadhavan Srinivasan PM_DERAT_MISS_2M,
118ac96588dSMadhavan Srinivasan PM_DTLB_MISS_2M,
119ac96588dSMadhavan Srinivasan PM_MRK_DTLB_MISS_1G,
120ac96588dSMadhavan Srinivasan PM_DTLB_MISS_4K,
121ac96588dSMadhavan Srinivasan PM_DERAT_MISS_1G,
122ac96588dSMadhavan Srinivasan PM_MRK_DERAT_MISS_2M,
123ac96588dSMadhavan Srinivasan PM_MRK_DTLB_MISS_4K,
124ac96588dSMadhavan Srinivasan PM_MRK_DTLB_MISS_16G,
125ac96588dSMadhavan Srinivasan PM_DTLB_MISS_64K,
126ac96588dSMadhavan Srinivasan PM_MRK_DERAT_MISS_1G,
127ac96588dSMadhavan Srinivasan PM_MRK_DTLB_MISS_64K,
128ac96588dSMadhavan Srinivasan PM_DISP_HELD_SYNC_HOLD,
129ac96588dSMadhavan Srinivasan PM_DTLB_MISS_16M,
130ac96588dSMadhavan Srinivasan PM_DTLB_MISS_1G,
131ac96588dSMadhavan Srinivasan PM_MRK_DTLB_MISS_16M,
132ac96588dSMadhavan Srinivasan };
133ac96588dSMadhavan Srinivasan
134a114aca5SMadhavan Srinivasan /* Table of alternatives, sorted by column 0 */
135a114aca5SMadhavan Srinivasan static const unsigned int power9_event_alternatives[][MAX_ALT] = {
1360dcad700SAthira Rajeev { PM_BR_2PATH, PM_BR_2PATH_ALT },
137a114aca5SMadhavan Srinivasan { PM_INST_DISP, PM_INST_DISP_ALT },
1383f0bd8daSAnton Blanchard { PM_RUN_CYC_ALT, PM_RUN_CYC },
13991e0bd1eSMadhavan Srinivasan { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT },
1400dcad700SAthira Rajeev { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
141a114aca5SMadhavan Srinivasan };
142a114aca5SMadhavan Srinivasan
power9_get_alternatives(u64 event,unsigned int flags,u64 alt[])143a114aca5SMadhavan Srinivasan static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
144a114aca5SMadhavan Srinivasan {
145a114aca5SMadhavan Srinivasan int num_alt = 0;
146a114aca5SMadhavan Srinivasan
14770a7e720SMadhavan Srinivasan num_alt = isa207_get_alternatives(event, alt,
14870a7e720SMadhavan Srinivasan ARRAY_SIZE(power9_event_alternatives), flags,
14970a7e720SMadhavan Srinivasan power9_event_alternatives);
150a114aca5SMadhavan Srinivasan
151a114aca5SMadhavan Srinivasan return num_alt;
152a114aca5SMadhavan Srinivasan }
153a114aca5SMadhavan Srinivasan
power9_check_attr_config(struct perf_event * ev)154d8a1d6c5SMadhavan Srinivasan static int power9_check_attr_config(struct perf_event *ev)
155d8a1d6c5SMadhavan Srinivasan {
156d8a1d6c5SMadhavan Srinivasan u64 val;
157d8a1d6c5SMadhavan Srinivasan u64 event = ev->attr.config;
158d8a1d6c5SMadhavan Srinivasan
159d8a1d6c5SMadhavan Srinivasan val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
160d8a1d6c5SMadhavan Srinivasan if (val == 0xC || isa3XX_check_attr_config(ev))
161d8a1d6c5SMadhavan Srinivasan return -EINVAL;
162d8a1d6c5SMadhavan Srinivasan
163d8a1d6c5SMadhavan Srinivasan return 0;
164d8a1d6c5SMadhavan Srinivasan }
165d8a1d6c5SMadhavan Srinivasan
166f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
167f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC);
168f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
169f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
17093fc5ca9SMadhavan Srinivasan GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL);
171f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
172f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
173f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN);
174ab4510e9SMadhavan Srinivasan GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS);
175ab4510e9SMadhavan Srinivasan GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
176f1fb60bfSMadhavan Srinivasan
177f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
178f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
179f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
180f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
181f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
182f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
183f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
184f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
185f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
186f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
187f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
18893fc5ca9SMadhavan Srinivasan CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
189f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
190f1fb60bfSMadhavan Srinivasan CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
191f1fb60bfSMadhavan Srinivasan
192f1fb60bfSMadhavan Srinivasan static struct attribute *power9_events_attr[] = {
193f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_PTR(PM_CYC),
194f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
195f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_PTR(PM_CMPLU_STALL),
196f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_PTR(PM_INST_CMPL),
19793fc5ca9SMadhavan Srinivasan GENERIC_EVENT_PTR(PM_BR_CMPL),
198f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
199f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_PTR(PM_LD_REF_L1),
200f1fb60bfSMadhavan Srinivasan GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
201ab4510e9SMadhavan Srinivasan GENERIC_EVENT_PTR(MEM_LOADS),
202ab4510e9SMadhavan Srinivasan GENERIC_EVENT_PTR(MEM_STORES),
203f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
204f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_LD_REF_L1),
205f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_L1_PREF),
206f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_ST_MISS_L1),
207f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
208f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_INST_FROM_L1),
209f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
210f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
211f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_DATA_FROM_L3),
212f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_L3_PREF_ALL),
213f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
21493fc5ca9SMadhavan Srinivasan CACHE_EVENT_PTR(PM_BR_CMPL),
215f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_DTLB_MISS),
216f1fb60bfSMadhavan Srinivasan CACHE_EVENT_PTR(PM_ITLB_MISS),
217f1fb60bfSMadhavan Srinivasan NULL
218f1fb60bfSMadhavan Srinivasan };
219f1fb60bfSMadhavan Srinivasan
2206b3a3e12SRohan McLure static const struct attribute_group power9_pmu_events_group = {
221f1fb60bfSMadhavan Srinivasan .name = "events",
222f1fb60bfSMadhavan Srinivasan .attrs = power9_events_attr,
223f1fb60bfSMadhavan Srinivasan };
2248c002dbdSMadhavan Srinivasan
22518201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(event, "config:0-51");
22618201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
22718201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(mark, "config:8");
22818201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(combine, "config:10-11");
22918201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(unit, "config:12-15");
23018201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(pmc, "config:16-19");
23118201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(cache_sel, "config:20-23");
23218201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(sample_mode, "config:24-28");
23318201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
23418201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
23518201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_start, "config:36-39");
23618201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
23718201b20SMadhavan Srinivasan PMU_FORMAT_ATTR(sdar_mode, "config:50-51");
23818201b20SMadhavan Srinivasan
23918201b20SMadhavan Srinivasan static struct attribute *power9_pmu_format_attr[] = {
24018201b20SMadhavan Srinivasan &format_attr_event.attr,
24118201b20SMadhavan Srinivasan &format_attr_pmcxsel.attr,
24218201b20SMadhavan Srinivasan &format_attr_mark.attr,
24318201b20SMadhavan Srinivasan &format_attr_combine.attr,
24418201b20SMadhavan Srinivasan &format_attr_unit.attr,
24518201b20SMadhavan Srinivasan &format_attr_pmc.attr,
24618201b20SMadhavan Srinivasan &format_attr_cache_sel.attr,
24718201b20SMadhavan Srinivasan &format_attr_sample_mode.attr,
24818201b20SMadhavan Srinivasan &format_attr_thresh_sel.attr,
24918201b20SMadhavan Srinivasan &format_attr_thresh_stop.attr,
25018201b20SMadhavan Srinivasan &format_attr_thresh_start.attr,
25118201b20SMadhavan Srinivasan &format_attr_thresh_cmp.attr,
25218201b20SMadhavan Srinivasan &format_attr_sdar_mode.attr,
25318201b20SMadhavan Srinivasan NULL,
25418201b20SMadhavan Srinivasan };
25518201b20SMadhavan Srinivasan
2566b3a3e12SRohan McLure static const struct attribute_group power9_pmu_format_group = {
25718201b20SMadhavan Srinivasan .name = "format",
25818201b20SMadhavan Srinivasan .attrs = power9_pmu_format_attr,
25918201b20SMadhavan Srinivasan };
26018201b20SMadhavan Srinivasan
2616320e693SAthira Rajeev static struct attribute *power9_pmu_caps_attrs[] = {
2626320e693SAthira Rajeev NULL
2636320e693SAthira Rajeev };
2646320e693SAthira Rajeev
2656320e693SAthira Rajeev static struct attribute_group power9_pmu_caps_group = {
2666320e693SAthira Rajeev .name = "caps",
2676320e693SAthira Rajeev .attrs = power9_pmu_caps_attrs,
2686320e693SAthira Rajeev };
2696320e693SAthira Rajeev
27018201b20SMadhavan Srinivasan static const struct attribute_group *power9_pmu_attr_groups[] = {
27118201b20SMadhavan Srinivasan &power9_pmu_format_group,
27218201b20SMadhavan Srinivasan &power9_pmu_events_group,
2736320e693SAthira Rajeev &power9_pmu_caps_group,
27418201b20SMadhavan Srinivasan NULL,
27518201b20SMadhavan Srinivasan };
27618201b20SMadhavan Srinivasan
2778c002dbdSMadhavan Srinivasan static int power9_generic_events[] = {
2788c002dbdSMadhavan Srinivasan [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
2798c002dbdSMadhavan Srinivasan [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
2808c002dbdSMadhavan Srinivasan [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
2818c002dbdSMadhavan Srinivasan [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
28293fc5ca9SMadhavan Srinivasan [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL,
2838c002dbdSMadhavan Srinivasan [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
2848c002dbdSMadhavan Srinivasan [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
2858c002dbdSMadhavan Srinivasan [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
2868c002dbdSMadhavan Srinivasan };
2878c002dbdSMadhavan Srinivasan
power9_bhrb_filter_map(u64 branch_sample_type)2888c002dbdSMadhavan Srinivasan static u64 power9_bhrb_filter_map(u64 branch_sample_type)
2898c002dbdSMadhavan Srinivasan {
2908c002dbdSMadhavan Srinivasan u64 pmu_bhrb_filter = 0;
2918c002dbdSMadhavan Srinivasan
2928c002dbdSMadhavan Srinivasan /* BHRB and regular PMU events share the same privilege state
2938c002dbdSMadhavan Srinivasan * filter configuration. BHRB is always recorded along with a
2948c002dbdSMadhavan Srinivasan * regular PMU event. As the privilege state filter is handled
2958c002dbdSMadhavan Srinivasan * in the basic PMC configuration of the accompanying regular
2968c002dbdSMadhavan Srinivasan * PMU event, we ignore any separate BHRB specific request.
2978c002dbdSMadhavan Srinivasan */
2988c002dbdSMadhavan Srinivasan
2998c002dbdSMadhavan Srinivasan /* No branch filter requested */
3008c002dbdSMadhavan Srinivasan if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
3018c002dbdSMadhavan Srinivasan return pmu_bhrb_filter;
3028c002dbdSMadhavan Srinivasan
3038c002dbdSMadhavan Srinivasan /* Invalid branch filter options - HW does not support */
3048c002dbdSMadhavan Srinivasan if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
3058c002dbdSMadhavan Srinivasan return -1;
3068c002dbdSMadhavan Srinivasan
3078c002dbdSMadhavan Srinivasan if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
3088c002dbdSMadhavan Srinivasan return -1;
3098c002dbdSMadhavan Srinivasan
3108c002dbdSMadhavan Srinivasan if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
3118c002dbdSMadhavan Srinivasan return -1;
3128c002dbdSMadhavan Srinivasan
3138c002dbdSMadhavan Srinivasan if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
3148c002dbdSMadhavan Srinivasan pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
3158c002dbdSMadhavan Srinivasan return pmu_bhrb_filter;
3168c002dbdSMadhavan Srinivasan }
3178c002dbdSMadhavan Srinivasan
3188c002dbdSMadhavan Srinivasan /* Every thing else is unsupported */
3198c002dbdSMadhavan Srinivasan return -1;
3208c002dbdSMadhavan Srinivasan }
3218c002dbdSMadhavan Srinivasan
power9_config_bhrb(u64 pmu_bhrb_filter)3228c002dbdSMadhavan Srinivasan static void power9_config_bhrb(u64 pmu_bhrb_filter)
3238c002dbdSMadhavan Srinivasan {
3243202e35eSRavi Bangoria pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK;
3253202e35eSRavi Bangoria
3268c002dbdSMadhavan Srinivasan /* Enable BHRB filter in PMU */
3278c002dbdSMadhavan Srinivasan mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
3288c002dbdSMadhavan Srinivasan }
3298c002dbdSMadhavan Srinivasan
3308c002dbdSMadhavan Srinivasan #define C(x) PERF_COUNT_HW_CACHE_##x
3318c002dbdSMadhavan Srinivasan
3328c002dbdSMadhavan Srinivasan /*
3338c002dbdSMadhavan Srinivasan * Table of generalized cache-related events.
3348c002dbdSMadhavan Srinivasan * 0 means not supported, -1 means nonsensical, other values
3358c002dbdSMadhavan Srinivasan * are event codes.
3368c002dbdSMadhavan Srinivasan */
3379d4fc86dSAthira Rajeev static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
3388c002dbdSMadhavan Srinivasan [ C(L1D) ] = {
3398c002dbdSMadhavan Srinivasan [ C(OP_READ) ] = {
3408c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
3418c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
3428c002dbdSMadhavan Srinivasan },
3438c002dbdSMadhavan Srinivasan [ C(OP_WRITE) ] = {
3448c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = 0,
3458c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
3468c002dbdSMadhavan Srinivasan },
3478c002dbdSMadhavan Srinivasan [ C(OP_PREFETCH) ] = {
3488c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = PM_L1_PREF,
3498c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = 0,
3508c002dbdSMadhavan Srinivasan },
3518c002dbdSMadhavan Srinivasan },
3528c002dbdSMadhavan Srinivasan [ C(L1I) ] = {
3538c002dbdSMadhavan Srinivasan [ C(OP_READ) ] = {
3548c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
3558c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
3568c002dbdSMadhavan Srinivasan },
3578c002dbdSMadhavan Srinivasan [ C(OP_WRITE) ] = {
3588c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
3598c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
3608c002dbdSMadhavan Srinivasan },
3618c002dbdSMadhavan Srinivasan [ C(OP_PREFETCH) ] = {
3628c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
3638c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = 0,
3648c002dbdSMadhavan Srinivasan },
3658c002dbdSMadhavan Srinivasan },
3668c002dbdSMadhavan Srinivasan [ C(LL) ] = {
3678c002dbdSMadhavan Srinivasan [ C(OP_READ) ] = {
3688c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
3698c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
3708c002dbdSMadhavan Srinivasan },
3718c002dbdSMadhavan Srinivasan [ C(OP_WRITE) ] = {
3723757cba8SMadhavan Srinivasan [ C(RESULT_ACCESS) ] = 0,
3733757cba8SMadhavan Srinivasan [ C(RESULT_MISS) ] = 0,
3748c002dbdSMadhavan Srinivasan },
3758c002dbdSMadhavan Srinivasan [ C(OP_PREFETCH) ] = {
3768c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
3778c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = 0,
3788c002dbdSMadhavan Srinivasan },
3798c002dbdSMadhavan Srinivasan },
3808c002dbdSMadhavan Srinivasan [ C(DTLB) ] = {
3818c002dbdSMadhavan Srinivasan [ C(OP_READ) ] = {
3828c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = 0,
3838c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = PM_DTLB_MISS,
3848c002dbdSMadhavan Srinivasan },
3858c002dbdSMadhavan Srinivasan [ C(OP_WRITE) ] = {
3868c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = -1,
3878c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
3888c002dbdSMadhavan Srinivasan },
3898c002dbdSMadhavan Srinivasan [ C(OP_PREFETCH) ] = {
3908c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = -1,
3918c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
3928c002dbdSMadhavan Srinivasan },
3938c002dbdSMadhavan Srinivasan },
3948c002dbdSMadhavan Srinivasan [ C(ITLB) ] = {
3958c002dbdSMadhavan Srinivasan [ C(OP_READ) ] = {
3968c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = 0,
3978c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = PM_ITLB_MISS,
3988c002dbdSMadhavan Srinivasan },
3998c002dbdSMadhavan Srinivasan [ C(OP_WRITE) ] = {
4008c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = -1,
4018c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
4028c002dbdSMadhavan Srinivasan },
4038c002dbdSMadhavan Srinivasan [ C(OP_PREFETCH) ] = {
4048c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = -1,
4058c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
4068c002dbdSMadhavan Srinivasan },
4078c002dbdSMadhavan Srinivasan },
4088c002dbdSMadhavan Srinivasan [ C(BPU) ] = {
4098c002dbdSMadhavan Srinivasan [ C(OP_READ) ] = {
41093fc5ca9SMadhavan Srinivasan [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
4118c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
4128c002dbdSMadhavan Srinivasan },
4138c002dbdSMadhavan Srinivasan [ C(OP_WRITE) ] = {
4148c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = -1,
4158c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
4168c002dbdSMadhavan Srinivasan },
4178c002dbdSMadhavan Srinivasan [ C(OP_PREFETCH) ] = {
4188c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = -1,
4198c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
4208c002dbdSMadhavan Srinivasan },
4218c002dbdSMadhavan Srinivasan },
4228c002dbdSMadhavan Srinivasan [ C(NODE) ] = {
4238c002dbdSMadhavan Srinivasan [ C(OP_READ) ] = {
4248c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = -1,
4258c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
4268c002dbdSMadhavan Srinivasan },
4278c002dbdSMadhavan Srinivasan [ C(OP_WRITE) ] = {
4288c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = -1,
4298c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
4308c002dbdSMadhavan Srinivasan },
4318c002dbdSMadhavan Srinivasan [ C(OP_PREFETCH) ] = {
4328c002dbdSMadhavan Srinivasan [ C(RESULT_ACCESS) ] = -1,
4338c002dbdSMadhavan Srinivasan [ C(RESULT_MISS) ] = -1,
4348c002dbdSMadhavan Srinivasan },
4358c002dbdSMadhavan Srinivasan },
4368c002dbdSMadhavan Srinivasan };
4378c002dbdSMadhavan Srinivasan
4388c002dbdSMadhavan Srinivasan #undef C
4398c002dbdSMadhavan Srinivasan
44018201b20SMadhavan Srinivasan static struct power_pmu power9_pmu = {
44118201b20SMadhavan Srinivasan .name = "POWER9",
44218201b20SMadhavan Srinivasan .n_counter = MAX_PMU_COUNTERS,
44318201b20SMadhavan Srinivasan .add_fields = ISA207_ADD_FIELDS,
4448c218578SMadhavan Srinivasan .test_adder = ISA207_TEST_ADDER,
44559029136SMadhavan Srinivasan .group_constraint_mask = CNST_CACHE_PMC4_MASK,
44659029136SMadhavan Srinivasan .group_constraint_val = CNST_CACHE_PMC4_VAL,
44718201b20SMadhavan Srinivasan .compute_mmcr = isa207_compute_mmcr,
44818201b20SMadhavan Srinivasan .config_bhrb = power9_config_bhrb,
44918201b20SMadhavan Srinivasan .bhrb_filter_map = power9_bhrb_filter_map,
45018201b20SMadhavan Srinivasan .get_constraint = isa207_get_constraint,
451a114aca5SMadhavan Srinivasan .get_alternatives = power9_get_alternatives,
452d148c94cSMadhavan Srinivasan .get_mem_data_src = isa207_get_mem_data_src,
453d148c94cSMadhavan Srinivasan .get_mem_weight = isa207_get_mem_weight,
45418201b20SMadhavan Srinivasan .disable_pmc = isa207_disable_pmc,
45518201b20SMadhavan Srinivasan .flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
45618201b20SMadhavan Srinivasan .n_generic = ARRAY_SIZE(power9_generic_events),
45718201b20SMadhavan Srinivasan .generic_events = power9_generic_events,
45818201b20SMadhavan Srinivasan .cache_events = &power9_cache_events,
45918201b20SMadhavan Srinivasan .attr_groups = power9_pmu_attr_groups,
46018201b20SMadhavan Srinivasan .bhrb_nr = 32,
461781fa481SAnju T Sudhakar .capabilities = PERF_PMU_CAP_EXTENDED_REGS,
462d8a1d6c5SMadhavan Srinivasan .check_attr_config = power9_check_attr_config,
46318201b20SMadhavan Srinivasan };
46418201b20SMadhavan Srinivasan
init_power9_pmu(void)465c49f5d88SNick Child int __init init_power9_pmu(void)
4668c002dbdSMadhavan Srinivasan {
467520ed5b0SMadhavan Srinivasan int rc = 0;
46864acab4eSMadhavan Srinivasan unsigned int pvr = mfspr(SPRN_PVR);
4698c002dbdSMadhavan Srinivasan
470*ec3eb9d9SRashmica Gupta if (PVR_VER(pvr) != PVR_POWER9)
4718c002dbdSMadhavan Srinivasan return -ENODEV;
4728c002dbdSMadhavan Srinivasan
47364acab4eSMadhavan Srinivasan /* Blacklist events */
47464acab4eSMadhavan Srinivasan if (!(pvr & PVR_POWER9_CUMULUS)) {
47564acab4eSMadhavan Srinivasan if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) {
47664acab4eSMadhavan Srinivasan power9_pmu.blacklist_ev = p9_dd21_bl_ev;
47764acab4eSMadhavan Srinivasan power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev);
478ac96588dSMadhavan Srinivasan } else if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 2)) {
479ac96588dSMadhavan Srinivasan power9_pmu.blacklist_ev = p9_dd22_bl_ev;
480ac96588dSMadhavan Srinivasan power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd22_bl_ev);
48164acab4eSMadhavan Srinivasan }
48264acab4eSMadhavan Srinivasan }
48364acab4eSMadhavan Srinivasan
484781fa481SAnju T Sudhakar /* Set the PERF_REG_EXTENDED_MASK here */
485781fa481SAnju T Sudhakar PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_300;
486781fa481SAnju T Sudhakar
48718201b20SMadhavan Srinivasan rc = register_power_pmu(&power9_pmu);
4888c002dbdSMadhavan Srinivasan if (rc)
4898c002dbdSMadhavan Srinivasan return rc;
4908c002dbdSMadhavan Srinivasan
4918c002dbdSMadhavan Srinivasan /* Tell userspace that EBB is supported */
4928c002dbdSMadhavan Srinivasan cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
4938c002dbdSMadhavan Srinivasan
4948c002dbdSMadhavan Srinivasan return 0;
4958c002dbdSMadhavan Srinivasan }
496