drivers/perf/riscv_pmu_sbi.c

122 #define C(x) PERF_COUNT_HW_CACHE_##x  macro
126 	[C(L1D)] = {
127 		[C(OP_READ)] = {
128 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
129 					C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
130 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
131 					C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
133 		[C(OP_WRITE)] = {
134 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
135 					C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
136 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
137 					C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
139 		[C(OP_PREFETCH)] = {
140 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
141 					C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
142 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
143 					C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
146 	[C(L1I)] = {
147 		[C(OP_READ)] = {
148 			[C(RESULT_ACCESS)] = {.hw_cache_event =	{C(RESULT_ACCESS),
149 					C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
150 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ),
151 					C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
153 		[C(OP_WRITE)] = {
154 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
155 					C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
156 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
157 					C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
159 		[C(OP_PREFETCH)] = {
160 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
161 					C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
162 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
163 					C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
166 	[C(LL)] = {
167 		[C(OP_READ)] = {
168 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
169 					C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
170 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
171 					C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
173 		[C(OP_WRITE)] = {
174 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
175 					C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
176 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
177 					C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
179 		[C(OP_PREFETCH)] = {
180 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
181 					C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
182 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
183 					C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}},
186 	[C(DTLB)] = {
187 		[C(OP_READ)] = {
188 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
189 					C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
190 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
191 					C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
193 		[C(OP_WRITE)] = {
194 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
195 					C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
196 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
197 					C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
199 		[C(OP_PREFETCH)] = {
200 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
201 					C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
202 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
203 					C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
206 	[C(ITLB)] = {
207 		[C(OP_READ)] = {
208 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
209 					C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
210 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
211 					C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
213 		[C(OP_WRITE)] = {
214 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
215 					C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
216 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
217 					C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
219 		[C(OP_PREFETCH)] = {
220 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
221 					C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
222 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
223 					C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
226 	[C(BPU)] = {
227 		[C(OP_READ)] = {
228 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
229 					C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
230 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
231 					C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
233 		[C(OP_WRITE)] = {
234 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
235 					C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
236 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
237 					C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
239 		[C(OP_PREFETCH)] = {
240 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
241 					C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
242 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
243 					C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}},
246 	[C(NODE)] = {
247 		[C(OP_READ)] = {
248 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
249 					C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
250 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
251 					C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
253 		[C(OP_WRITE)] = {
254 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
255 					C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
256 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
257 					C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
259 		[C(OP_PREFETCH)] = {
260 			[C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
261 					C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},
262 			[C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
263 					C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}},