Lines Matching refs:C
178 #define C(x) PERF_COUNT_HW_CACHE_##x macro
185 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
186 [ C(L1D) ] = {
187 [ C(OP_READ) ] = {
188 [ C(RESULT_ACCESS) ] = 0,
189 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
191 [ C(OP_WRITE) ] = {
192 [ C(RESULT_ACCESS) ] = 0,
193 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
195 [ C(OP_PREFETCH) ] = {
196 [ C(RESULT_ACCESS) ] = 0,
197 [ C(RESULT_MISS) ] = 0,
200 [ C(L1I) ] = {
201 [ C(OP_READ) ] = {
202 [ C(RESULT_ACCESS) ] = 0,
203 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
205 [ C(OP_WRITE) ] = {
206 [ C(RESULT_ACCESS) ] = 0,
207 [ C(RESULT_MISS) ] = -1,
209 [ C(OP_PREFETCH) ] = {
210 [ C(RESULT_ACCESS) ] = 0,
211 [ C(RESULT_MISS) ] = 0,
214 [ C(LL) ] = {
215 [ C(OP_READ) ] = {
216 [ C(RESULT_ACCESS) ] = 0,
217 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
219 [ C(OP_WRITE) ] = {
220 [ C(RESULT_ACCESS) ] = 0,
221 [ C(RESULT_MISS) ] = 0,
223 [ C(OP_PREFETCH) ] = {
224 [ C(RESULT_ACCESS) ] = 0,
225 [ C(RESULT_MISS) ] = 0,
228 [ C(DTLB) ] = {
229 [ C(OP_READ) ] = {
230 [ C(RESULT_ACCESS) ] = 0,
231 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
233 [ C(OP_WRITE) ] = {
234 [ C(RESULT_ACCESS) ] = -1,
235 [ C(RESULT_MISS) ] = -1,
237 [ C(OP_PREFETCH) ] = {
238 [ C(RESULT_ACCESS) ] = -1,
239 [ C(RESULT_MISS) ] = -1,
242 [ C(ITLB) ] = {
243 [ C(OP_READ) ] = {
244 [ C(RESULT_ACCESS) ] = 0,
245 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
247 [ C(OP_WRITE) ] = {
248 [ C(RESULT_ACCESS) ] = -1,
249 [ C(RESULT_MISS) ] = -1,
251 [ C(OP_PREFETCH) ] = {
252 [ C(RESULT_ACCESS) ] = -1,
253 [ C(RESULT_MISS) ] = -1,
256 [ C(BPU) ] = {
257 [ C(OP_READ) ] = {
258 [ C(RESULT_ACCESS) ] = 0,
259 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
261 [ C(OP_WRITE) ] = {
262 [ C(RESULT_ACCESS) ] = -1,
263 [ C(RESULT_MISS) ] = -1,
265 [ C(OP_PREFETCH) ] = {
266 [ C(RESULT_ACCESS) ] = -1,
267 [ C(RESULT_MISS) ] = -1,
270 [ C(NODE) ] = {
271 [ C(OP_READ) ] = {
272 [ C(RESULT_ACCESS) ] = -1,
273 [ C(RESULT_MISS) ] = -1,
275 [ C(OP_WRITE) ] = {
276 [ C(RESULT_ACCESS) ] = -1,
277 [ C(RESULT_MISS) ] = -1,
279 [ C(OP_PREFETCH) ] = {
280 [ C(RESULT_ACCESS) ] = -1,
281 [ C(RESULT_MISS) ] = -1,
286 #undef C