/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt8195-apmixedsys.c | 62 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0, 64 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0, 66 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0, 68 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0, 80 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0, 94 PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0, 96 PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0, 98 PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0, 100 PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0, 104 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0, [all …]
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H A D | clk-mt8188-apmixedsys.c | 61 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0, 63 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0, 65 PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0, 67 PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0, 73 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0, 79 PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0, 81 PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0, 83 PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0, 85 PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0, 87 PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0, [all …]
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H A D | clk-mt8135-apmixedsys.c | 20 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… macro 38 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0), 39 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0), 40 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2… 41 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23… 42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, … 43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0), 44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0), 45 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), 46 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0), [all …]
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H A D | clk-mt8186-apmixedsys.c | 19 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ macro 55 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0, 61 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0, 63 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0, 65 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0, 67 PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0, 69 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0, 71 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0, 73 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0, 75 PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0, [all …]
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H A D | clk-mt2712-apmixedsys.c | 44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro 80 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100, 82 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100, 86 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100, 88 PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100, 90 PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100, 92 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100, 94 PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100, 96 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100, 98 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100, [all …]
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H A D | clk-mt8173-apmixedsys.c | 44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro 61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO, 63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO, 65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21, 67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7, 71 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0), 72 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0), 73 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0), 74 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0), 76 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0), [all …]
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H A D | clk-mt7986-apmixed.c | 36 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro 43 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32, 45 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32, 47 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32, 49 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x0, 0, 32, 51 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x0, 0, 53 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x0, 0, 32, 55 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x0, 0, 32, 0x0260, 57 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x0, 0, 32,
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H A D | clk-mt7981-apmixed.c | 38 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro 45 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO, 47 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, 49 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, 51 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32, 53 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32, 55 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32, 57 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 59 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
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H A D | clk-mt7622-apmixedsys.c | 41 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro 59 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0, 61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0, 63 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0, 65 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0, 67 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0, 69 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0, 71 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0, 73 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0, 75 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
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H A D | clk-mt6795-apmixedsys.c | 26 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro 47 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO, 49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 51 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR, 53 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0), 54 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0), 55 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0), 56 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0), 57 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0), 59 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0), [all …]
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H A D | clk-mt8365-apmixedsys.c | 45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro 85 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001, 87 PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001, 91 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22, 93 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22, 95 PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32, 97 PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32, 99 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22, 103 PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22,
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H A D | clk-mt8167-apmixedsys.c | 42 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro 59 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, 61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, 63 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, 67 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, 69 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, 71 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0, 73 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0,
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H A D | clk-mt8183-apmixedsys.c | 81 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ macro 117 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0, 120 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0, 123 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0, 129 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0, 131 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0, 133 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0, 136 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0, 138 PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0,
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H A D | clk-mt8516-apmixedsys.c | 43 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro 60 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, 62 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, 64 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, 68 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, 70 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
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H A D | clk-mt8195-apusys_pll.c | 28 #define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \ macro 53 PLL(CLK_APUSYS_PLL_APUPLL, "apusys_pll_apupll", 0x008, 0x014, 0x00c, 0x00c), 54 PLL(CLK_APUSYS_PLL_NPUPLL, "apusys_pll_npupll", 0x018, 0x024, 0x01c, 0x01c), 55 PLL(CLK_APUSYS_PLL_APUPLL1, "apusys_pll_apupll1", 0x028, 0x034, 0x02c, 0x02c), 56 PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0x03c, 0x03c),
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | qcom,mmcc.yaml | 83 - description: PLL 3 clock 84 - description: PLL 3 Vote clock 89 - description: HDMI phy PLL clock 149 - description: HDMI phy PLL clock 188 - description: HDMI phy PLL clock 232 - description: Global PLL 0 clock 239 - description: HDMI phy PLL clock 263 - description: Global PLL 0 clock 269 - description: HDMI phy PLL clock 292 - description: Global PLL 0 clock [all …]
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H A D | qcom,a53pll.yaml | 7 title: Qualcomm A53 PLL clock 13 The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for 50 # Example 1 - A53 PLL found on MSM8916 devices 57 # Example 2 - A53 PLL found on IPQ6018 devices
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H A D | ti,cdce925.yaml | 15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913 16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925 17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937 18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949 54 "^PLL[1-4]$": 97 /* PLL options to get SSC 1% centered */
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H A D | xgene.txt | 9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock 10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock 13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock 14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock 16 Required properties for SoC or PCP PLL clocks: 17 - reg : shall be the physical PLL register address for the pll clock. 21 - clock-output-names : shall be the name of the PLL referenced by derive 23 Optional properties for PLL clocks: 24 - clock-names : shall be the name of the PLL. If missing, use the device name. 32 Optional properties for PLL clocks:
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H A D | dove-divider-clock.txt | 1 PLL divider based Dove clocks 3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide 18 - reg : shall be the register address of the Core PLL and Clock Divider 20 Core PLL and Clock Divider Control 1 register. Thus, it will have
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H A D | baikal,bt1-ccu-pll.yaml | 8 title: Baikal-T1 Clock Control Unit PLL 52 with an interface wrapper (so called safe PLL' clocks switcher) to simplify 53 the PLL configuration procedure. The PLLs work as depicted on the next 71 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT - 72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment 73 the binding supports the PLL dividers configuration in accordance with a 81 The CCU PLL dts-node uses the common clock bindings with no custom 83 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the 113 # Clock Control Unit PLL node:
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/openbmc/u-boot/doc/device-tree-bindings/clock/ |
H A D | st,stm32h7-rcc.txt | 29 Please see PLL section below. 65 STM32H7 PLL 68 The VCO of STM32 PLL could be reprensented like this: 79 When the PLL is configured in integer mode: 82 When the PLL is configured in fractional mode: 107 - st,pllrge: PLL input frequency range 108 - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz 109 - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz 110 - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz 111 - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz
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/openbmc/u-boot/drivers/clk/at91/ |
H A D | Kconfig | 9 PLLA, UTMI PLL. Clocks can also be a source clock of other 16 bool "Support UTMI PLL Clock" 23 This option is used to enable the AT91 UTMI PLL clock 25 output of 480 MHz UTMI PLL, The souce clock of the UTMI 26 PLL is the main clock, so the main clock must select the 35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
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/openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
H A D | pll.txt | 1 Binding for TI DaVinci PLL Controllers 3 The PLL provides clocks to most of the components on the SoC. In addition 4 to the PLL itself, this controller also contains bypasses, gates, dividers, 26 Describes the main PLL clock output (before POSTDIV). The node name must 41 Describes the AUXCLK output of the PLL. The node name must be "auxclk". 48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | tas2552.txt | 19 internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM 20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK. 22 defined values to select and configure the PLL and PDM reference clocks.
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