1938cc3a1SLoc HoDevice Tree Clock bindings for APM X-Gene 2938cc3a1SLoc Ho 3938cc3a1SLoc HoThis binding uses the common clock binding[1]. 4938cc3a1SLoc Ho 5938cc3a1SLoc Ho[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6938cc3a1SLoc Ho 7938cc3a1SLoc HoRequired properties: 8938cc3a1SLoc Ho- compatible : shall be one of the following: 9938cc3a1SLoc Ho "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock 10938cc3a1SLoc Ho "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock 11405f27beSHoan Tran "apm,xgene-pmd-clock" - for a X-Gene PMD clock 12938cc3a1SLoc Ho "apm,xgene-device-clock" - for a X-Gene device clock 137b63c567SLoc Ho "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock 147b63c567SLoc Ho "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock 15938cc3a1SLoc Ho 16938cc3a1SLoc HoRequired properties for SoC or PCP PLL clocks: 17938cc3a1SLoc Ho- reg : shall be the physical PLL register address for the pll clock. 18938cc3a1SLoc Ho- clocks : shall be the input parent clock phandle for the clock. This should 19938cc3a1SLoc Ho be the reference clock. 20938cc3a1SLoc Ho- #clock-cells : shall be set to 1. 21938cc3a1SLoc Ho- clock-output-names : shall be the name of the PLL referenced by derive 22938cc3a1SLoc Ho clock. 23938cc3a1SLoc HoOptional properties for PLL clocks: 24938cc3a1SLoc Ho- clock-names : shall be the name of the PLL. If missing, use the device name. 25938cc3a1SLoc Ho 26405f27beSHoan TranRequired properties for PMD clocks: 27405f27beSHoan Tran- reg : shall be the physical register address for the pmd clock. 28405f27beSHoan Tran- clocks : shall be the input parent clock phandle for the clock. 29405f27beSHoan Tran- #clock-cells : shall be set to 1. 30405f27beSHoan Tran- clock-output-names : shall be the name of the clock referenced by derive 31405f27beSHoan Tran clock. 32405f27beSHoan TranOptional properties for PLL clocks: 33405f27beSHoan Tran- clock-names : shall be the name of the clock. If missing, use the device name. 34405f27beSHoan Tran 35938cc3a1SLoc HoRequired properties for device clocks: 36938cc3a1SLoc Ho- reg : shall be a list of address and length pairs describing the CSR 37938cc3a1SLoc Ho reset and/or the divider. Either may be omitted, but at least 38938cc3a1SLoc Ho one must be present. 39938cc3a1SLoc Ho - reg-names : shall be a string list describing the reg resource. This 40938cc3a1SLoc Ho may include "csr-reg" and/or "div-reg". If this property 41938cc3a1SLoc Ho is not present, the reg property is assumed to describe 42938cc3a1SLoc Ho only "csr-reg". 43938cc3a1SLoc Ho- clocks : shall be the input parent clock phandle for the clock. 44938cc3a1SLoc Ho- #clock-cells : shall be set to 1. 45938cc3a1SLoc Ho- clock-output-names : shall be the name of the device referenced. 46938cc3a1SLoc HoOptional properties for device clocks: 47938cc3a1SLoc Ho- clock-names : shall be the name of the device clock. If missing, use the 48938cc3a1SLoc Ho device name. 49938cc3a1SLoc Ho- csr-offset : Offset to the CSR reset register from the reset address base. 50938cc3a1SLoc Ho Default is 0. 51938cc3a1SLoc Ho- csr-mask : CSR reset mask bit. Default is 0xF. 52938cc3a1SLoc Ho- enable-offset : Offset to the enable register from the reset address base. 53938cc3a1SLoc Ho Default is 0x8. 54938cc3a1SLoc Ho- enable-mask : CSR enable mask bit. Default is 0xF. 55938cc3a1SLoc Ho- divider-offset : Offset to the divider CSR register from the divider base. 56938cc3a1SLoc Ho Default is 0x0. 57938cc3a1SLoc Ho- divider-width : Width of the divider register. Default is 0. 58938cc3a1SLoc Ho- divider-shift : Bit shift of the divider register. Default is 0. 59938cc3a1SLoc Ho 60938cc3a1SLoc HoFor example: 61938cc3a1SLoc Ho 62938cc3a1SLoc Ho pcppll: pcppll@17000100 { 63938cc3a1SLoc Ho compatible = "apm,xgene-pcppll-clock"; 64938cc3a1SLoc Ho #clock-cells = <1>; 65938cc3a1SLoc Ho clocks = <&refclk 0>; 66938cc3a1SLoc Ho clock-names = "pcppll"; 67938cc3a1SLoc Ho reg = <0x0 0x17000100 0x0 0x1000>; 68938cc3a1SLoc Ho clock-output-names = "pcppll"; 69938cc3a1SLoc Ho type = <0>; 70938cc3a1SLoc Ho }; 71938cc3a1SLoc Ho 72405f27beSHoan Tran pmd0clk: pmd0clk@7e200200 { 73405f27beSHoan Tran compatible = "apm,xgene-pmd-clock"; 74405f27beSHoan Tran #clock-cells = <1>; 75405f27beSHoan Tran clocks = <&pmdpll 0>; 76405f27beSHoan Tran reg = <0x0 0x7e200200 0x0 0x10>; 77405f27beSHoan Tran clock-output-names = "pmd0clk"; 78405f27beSHoan Tran }; 79405f27beSHoan Tran 80938cc3a1SLoc Ho socpll: socpll@17000120 { 81938cc3a1SLoc Ho compatible = "apm,xgene-socpll-clock"; 82938cc3a1SLoc Ho #clock-cells = <1>; 83938cc3a1SLoc Ho clocks = <&refclk 0>; 84938cc3a1SLoc Ho clock-names = "socpll"; 85938cc3a1SLoc Ho reg = <0x0 0x17000120 0x0 0x1000>; 86938cc3a1SLoc Ho clock-output-names = "socpll"; 87938cc3a1SLoc Ho type = <1>; 88938cc3a1SLoc Ho }; 89938cc3a1SLoc Ho 90938cc3a1SLoc Ho qmlclk: qmlclk { 91938cc3a1SLoc Ho compatible = "apm,xgene-device-clock"; 92938cc3a1SLoc Ho #clock-cells = <1>; 93938cc3a1SLoc Ho clocks = <&socplldiv2 0>; 94938cc3a1SLoc Ho clock-names = "qmlclk"; 95938cc3a1SLoc Ho reg = <0x0 0x1703C000 0x0 0x1000>; 96938cc3a1SLoc Ho reg-name = "csr-reg"; 97938cc3a1SLoc Ho clock-output-names = "qmlclk"; 98938cc3a1SLoc Ho }; 99938cc3a1SLoc Ho 100938cc3a1SLoc Ho ethclk: ethclk { 101938cc3a1SLoc Ho compatible = "apm,xgene-device-clock"; 102938cc3a1SLoc Ho #clock-cells = <1>; 103938cc3a1SLoc Ho clocks = <&socplldiv2 0>; 104938cc3a1SLoc Ho clock-names = "ethclk"; 105938cc3a1SLoc Ho reg = <0x0 0x17000000 0x0 0x1000>; 106938cc3a1SLoc Ho reg-names = "div-reg"; 107938cc3a1SLoc Ho divider-offset = <0x238>; 108938cc3a1SLoc Ho divider-width = <0x9>; 109938cc3a1SLoc Ho divider-shift = <0x0>; 110938cc3a1SLoc Ho clock-output-names = "ethclk"; 111938cc3a1SLoc Ho }; 112938cc3a1SLoc Ho 113938cc3a1SLoc Ho apbclk: apbclk { 114938cc3a1SLoc Ho compatible = "apm,xgene-device-clock"; 115938cc3a1SLoc Ho #clock-cells = <1>; 116938cc3a1SLoc Ho clocks = <&ahbclk 0>; 117938cc3a1SLoc Ho clock-names = "apbclk"; 118938cc3a1SLoc Ho reg = <0x0 0x1F2AC000 0x0 0x1000 119938cc3a1SLoc Ho 0x0 0x1F2AC000 0x0 0x1000>; 120938cc3a1SLoc Ho reg-names = "csr-reg", "div-reg"; 121938cc3a1SLoc Ho csr-offset = <0x0>; 122938cc3a1SLoc Ho csr-mask = <0x200>; 123938cc3a1SLoc Ho enable-offset = <0x8>; 124938cc3a1SLoc Ho enable-mask = <0x200>; 125938cc3a1SLoc Ho divider-offset = <0x10>; 126938cc3a1SLoc Ho divider-width = <0x2>; 127938cc3a1SLoc Ho divider-shift = <0x0>; 128938cc3a1SLoc Ho flags = <0x8>; 129938cc3a1SLoc Ho clock-output-names = "apbclk"; 130938cc3a1SLoc Ho }; 131938cc3a1SLoc Ho 132