19e5935c0SWenyou Yangconfig CLK_AT91 29e5935c0SWenyou Yang bool "AT91 clock drivers" 39e5935c0SWenyou Yang depends on CLK 46cadaa04SWenyou Yang select MISC 59e5935c0SWenyou Yang help 69e5935c0SWenyou Yang This option is used to enable the AT91 clock driver. 79e5935c0SWenyou Yang The driver supports the AT91 clock generator, including 89e5935c0SWenyou Yang the oscillators and PLLs, such as main clock, slow clock, 99e5935c0SWenyou Yang PLLA, UTMI PLL. Clocks can also be a source clock of other 109e5935c0SWenyou Yang clocks a tree structure, such as master clock, usb device 119e5935c0SWenyou Yang clock, matrix clock and generic clock. 129e5935c0SWenyou Yang Devices can use a common clock API to request a particular 139e5935c0SWenyou Yang clock, enable it and get its rate. 149e5935c0SWenyou Yang 159e5935c0SWenyou Yangconfig AT91_UTMI 169e5935c0SWenyou Yang bool "Support UTMI PLL Clock" 179e0eb012SWenyou Yang depends on CLK_AT91 18e7c83154SWenyou Yang select REGMAP 199e0eb012SWenyou Yang select SPL_REGMAP if SPL_DM 20e7c83154SWenyou Yang select SYSCON 219e0eb012SWenyou Yang select SPL_SYSCON if SPL_DM 229e5935c0SWenyou Yang help 239e5935c0SWenyou Yang This option is used to enable the AT91 UTMI PLL clock 249e5935c0SWenyou Yang driver. It is the clock provider of USB, and UPLLCK is the 259e5935c0SWenyou Yang output of 480 MHz UTMI PLL, The souce clock of the UTMI 269e5935c0SWenyou Yang PLL is the main clock, so the main clock must select the 279e5935c0SWenyou Yang fast crystal oscillator to meet the frequency accuracy 289e5935c0SWenyou Yang required by USB. 299e5935c0SWenyou Yang 30*cb0cb1b0SWenyou Yangconfig AT91_USB_CLK 31*cb0cb1b0SWenyou Yang bool "Support USB OHCI Input Clock" 32*cb0cb1b0SWenyou Yang depends on CLK_AT91 33*cb0cb1b0SWenyou Yang help 34*cb0cb1b0SWenyou Yang This option is used to enable the USB Input Clock, from 35*cb0cb1b0SWenyou Yang the device tree, configure the USBS bit (PLLA or UTMI PLL) 36*cb0cb1b0SWenyou Yang and USBDIV field of the PMC_USB register. 37*cb0cb1b0SWenyou Yang 389e5935c0SWenyou Yangconfig AT91_H32MX 399e5935c0SWenyou Yang bool "Support H32MX 32-bit Matrix Clock" 409e5935c0SWenyou Yang depends on CLK_AT91 419e5935c0SWenyou Yang help 429e5935c0SWenyou Yang This option is used to enable the AT91 H32MX matrixes 439e5935c0SWenyou Yang clock driver. There are H64MX and H32MX matrixes clocks, 449e5935c0SWenyou Yang H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit 459e5935c0SWenyou Yang matrix clock is to be configured as MCK if MCK does not 469e5935c0SWenyou Yang exceed 83 MHz, else it is to be configured as MCK/2. 479e5935c0SWenyou Yang 489e5935c0SWenyou Yangconfig AT91_GENERIC_CLK 499e5935c0SWenyou Yang bool "Support Generic Clock" 509e5935c0SWenyou Yang depends on CLK_AT91 519e5935c0SWenyou Yang help 529e5935c0SWenyou Yang This option is used to enable the AT91 generic clock 539e5935c0SWenyou Yang driver. Some peripherals may need a second clock source 549e5935c0SWenyou Yang that may be different from the system clock. This second 559e5935c0SWenyou Yang clock is the generic clock (GCLK) and is managed by 569e5935c0SWenyou Yang the PMC via PMC_PCR register. 57