1b6e37ce2SDavid LechnerBinding for TI DaVinci PLL Controllers
2b6e37ce2SDavid Lechner
3b6e37ce2SDavid LechnerThe PLL provides clocks to most of the components on the SoC. In addition
4b6e37ce2SDavid Lechnerto the PLL itself, this controller also contains bypasses, gates, dividers,
5b6e37ce2SDavid Lechneran multiplexers for various clock signals.
6b6e37ce2SDavid Lechner
7b6e37ce2SDavid LechnerRequired properties:
8b6e37ce2SDavid Lechner- compatible: shall be one of:
9b6e37ce2SDavid Lechner	- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
10b6e37ce2SDavid Lechner	- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
11b6e37ce2SDavid Lechner- reg: physical base address and size of the controller's register area.
12b6e37ce2SDavid Lechner- clocks: phandles corresponding to the clock names
13b6e37ce2SDavid Lechner- clock-names: names of the clock sources - depends on compatible string
14b6e37ce2SDavid Lechner	- for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15b6e37ce2SDavid Lechner	- for "ti,da850-pll1", shall be "clksrc"
16b6e37ce2SDavid Lechner
17b6e37ce2SDavid LechnerOptional properties:
18*12e5bde1SSlark Xiao- ti,clkmode-square-wave: Indicates that the board is supplying a square
19b6e37ce2SDavid Lechner	wave input on the OSCIN pin instead of using a crystal oscillator.
20b6e37ce2SDavid Lechner	This property is only valid when compatible = "ti,da850-pll0".
21b6e37ce2SDavid Lechner
22b6e37ce2SDavid Lechner
23b6e37ce2SDavid LechnerOptional child nodes:
24b6e37ce2SDavid Lechner
25b6e37ce2SDavid Lechnerpllout
26b6e37ce2SDavid Lechner	Describes the main PLL clock output (before POSTDIV). The node name must
27b6e37ce2SDavid Lechner	be "pllout".
28b6e37ce2SDavid Lechner
29b6e37ce2SDavid Lechner	Required properties:
30b6e37ce2SDavid Lechner	- #clock-cells: shall be 0
31b6e37ce2SDavid Lechner
32b6e37ce2SDavid Lechnersysclk
33b6e37ce2SDavid Lechner	Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
34b6e37ce2SDavid Lechner	domains. The node name must be "sysclk". Consumers of this node should
35b6e37ce2SDavid Lechner	use "n" in "SYSCLKn" as the index parameter for the clock cell.
36b6e37ce2SDavid Lechner
37b6e37ce2SDavid Lechner	Required properties:
38b6e37ce2SDavid Lechner	- #clock-cells: shall be 1
39b6e37ce2SDavid Lechner
40b6e37ce2SDavid Lechnerauxclk
41b6e37ce2SDavid Lechner	Describes the AUXCLK output of the PLL. The node name must be "auxclk".
42b6e37ce2SDavid Lechner	This child node is only valid when compatible = "ti,da850-pll0".
43b6e37ce2SDavid Lechner
44b6e37ce2SDavid Lechner	Required properties:
45b6e37ce2SDavid Lechner	- #clock-cells: shall be 0
46b6e37ce2SDavid Lechner
47b6e37ce2SDavid Lechnerobsclk
48b6e37ce2SDavid Lechner	Describes the OBSCLK output of the PLL. The node name must be "obsclk".
49b6e37ce2SDavid Lechner
50b6e37ce2SDavid Lechner	Required properties:
51b6e37ce2SDavid Lechner	- #clock-cells: shall be 0
52b6e37ce2SDavid Lechner
53b6e37ce2SDavid Lechner
54b6e37ce2SDavid LechnerExamples:
55b6e37ce2SDavid Lechner
56b6e37ce2SDavid Lechner	pll0: clock-controller@11000 {
57b6e37ce2SDavid Lechner		compatible = "ti,da850-pll0";
58b6e37ce2SDavid Lechner		reg = <0x11000 0x1000>;
59b6e37ce2SDavid Lechner		clocks = <&ref_clk>, <&pll1_sysclk 3>;
60b6e37ce2SDavid Lechner		clock-names = "clksrc", "extclksrc";
61b6e37ce2SDavid Lechner		ti,clkmode-square-wave;
62b6e37ce2SDavid Lechner
63b6e37ce2SDavid Lechner		pll0_pllout: pllout {
64b6e37ce2SDavid Lechner			#clock-cells = <0>;
65b6e37ce2SDavid Lechner		};
66b6e37ce2SDavid Lechner
67b6e37ce2SDavid Lechner		pll0_sysclk: sysclk {
68b6e37ce2SDavid Lechner			#clock-cells = <1>;
69b6e37ce2SDavid Lechner		};
70b6e37ce2SDavid Lechner
71b6e37ce2SDavid Lechner		pll0_auxclk: auxclk {
72b6e37ce2SDavid Lechner			#clock-cells = <0>;
73b6e37ce2SDavid Lechner		};
74b6e37ce2SDavid Lechner
75b6e37ce2SDavid Lechner		pll0_obsclk: obsclk {
76b6e37ce2SDavid Lechner			#clock-cells = <0>;
77b6e37ce2SDavid Lechner		};
78b6e37ce2SDavid Lechner	};
79b6e37ce2SDavid Lechner
80b6e37ce2SDavid Lechner	pll1: clock-controller@21a000 {
81b6e37ce2SDavid Lechner		compatible = "ti,da850-pll1";
82b6e37ce2SDavid Lechner		reg = <0x21a000 0x1000>;
83b6e37ce2SDavid Lechner		clocks = <&ref_clk>;
84b6e37ce2SDavid Lechner		clock-names = "clksrc";
85b6e37ce2SDavid Lechner
86b6e37ce2SDavid Lechner		pll0_sysclk: sysclk {
87b6e37ce2SDavid Lechner			#clock-cells = <1>;
88b6e37ce2SDavid Lechner		};
89b6e37ce2SDavid Lechner
90b6e37ce2SDavid Lechner		pll0_obsclk: obsclk {
91b6e37ce2SDavid Lechner			#clock-cells = <0>;
92b6e37ce2SDavid Lechner		};
93b6e37ce2SDavid Lechner	};
94b6e37ce2SDavid Lechner
95b6e37ce2SDavid LechnerAlso see:
96b6e37ce2SDavid Lechner- Documentation/devicetree/bindings/clock/clock-bindings.txt
97