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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
23 - items:
24 - enum:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zcu1275-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1275
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
17 model = "ZynqMP ZCU1275 RevA";
18 compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
28 stdout-path = "serial0:115200n8";
48 compatible = "m25p80", "jedec,spi-nor";
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H A Dzynqmp-zc1254-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1254
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
17 model = "ZynqMP ZC1254 RevA";
18 compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
28 stdout-path = "serial0:115200n8";
44 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
[all …]
H A Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1232
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP ZC1232 RevA";
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
27 stdout-path = "serial0:115200n8";
43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
[all …]
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
117 phy-mode = "rgmii-id";
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H A Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
17 model = "ZynqMP zc1751-xm017-dc3 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
[all …]
/openbmc/linux/drivers/clk/zynqmp/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
4 obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zc1254-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1254
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
17 model = "ZynqMP ZC1254 RevA";
18 compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
28 stdout-path = "serial0:115200n8";
44 compatible = "m25p80", "spi-flash"; /* 32MB */
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H A Dzynqmp-zc1275-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1275
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
17 model = "ZynqMP ZC1275 RevA";
18 compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
28 stdout-path = "serial0:115200n8";
44 compatible = "m25p80", "spi-flash"; /* 32MB */
[all …]
H A Dzynqmp-zc1275-revB.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP ZC1275 RevB
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
17 model = "ZynqMP ZC1275 RevB";
18 compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
29 stdout-path = "serial0:115200n8";
45 compatible = "m25p80", "spi-flash"; /* 32MB */
46 #address-cells = <1>;
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm015-dc1 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
76 phy-handle = <&phy0>;
[all …]
H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm019-dc5 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
31 stdout-path = "serial0:115200n8";
74 phy-handle = <&phy0>;
[all …]
H A Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1232
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
17 model = "ZynqMP ZC1232 RevA";
18 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
28 stdout-path = "serial0:115200n8";
[all …]
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
37 stdout-path = "serial0:115200n8";
128 phy-mode = "rgmii-id";
[all …]
H A Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2018, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm017-dc3 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
77 phy-handle = <&phy0>;
[all …]
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm016-dc2 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
35 stdout-path = "serial0:115200n8";
86 phy-handle = <&phy0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxlnx,zynqmp-dma-1.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
20 - $ref: ../dma-controller.yaml#
[all …]
/openbmc/u-boot/drivers/clk/
H A DKconfig3 config CLK config
15 depends on CLK && SPL && SPL_DM
21 used as U-Boot proper.
25 depends on CLK && TPL_DM
31 used as U-Boot proper.
35 depends on CLK && ARCH_BMIPS
43 depends on CLK
51 depends on CLK && (STM32F7 || STM32F4)
59 depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL
67 depends on CLK
[all …]
H A Dclk_zynqmp.c1 // SPDX-License-Identifier: GPL-2.0+
3 * ZynqMP clock driver
10 #include <clk-uclass.h>
11 #include <clk.h>
241 debug("Invalid clk id%d\n", id); in zynqmp_clk_get_register()
323 return priv->video_clk; in zynqmp_clk_get_pll_src()
325 return priv->pss_alt_ref_clk; in zynqmp_clk_get_pll_src()
327 return priv->aux_ref_clk; in zynqmp_clk_get_pll_src()
329 return priv->gt_crx_ref_clk; in zynqmp_clk_get_pll_src()
332 return priv->ps_clk_freq; in zynqmp_clk_get_pll_src()
[all …]
/openbmc/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dpsub.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * ZynqMP DPSUB Subsystem Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
15 struct clk;
43 * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
62 struct clk *apb_clk;
63 struct clk *vid_clk;
65 struct clk *aud_clk;
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-zynqmp-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - xlnx,versal-qspi-1.0
19 - xlnx,zynqmp-qspi-1.0
27 clock-names:
29 - const: ref_clk
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
24 "#size-cells":
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]

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