1a5b5b45fSManish Narani# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2a5b5b45fSManish Narani%YAML 1.2 3a5b5b45fSManish Narani--- 4a5b5b45fSManish Narani$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml# 5a5b5b45fSManish Narani$schema: http://devicetree.org/meta-schemas/core.yaml# 6a5b5b45fSManish Narani 7a5b5b45fSManish Naranititle: Xilinx SuperSpeed DWC3 USB SoC controller 8a5b5b45fSManish Narani 9a5b5b45fSManish Naranimaintainers: 10*067bf44dSMichal Simek - Piyush Mehta <piyush.mehta@amd.com> 11a5b5b45fSManish Narani 12a5b5b45fSManish Naraniproperties: 13a5b5b45fSManish Narani compatible: 14a5b5b45fSManish Narani items: 15a5b5b45fSManish Narani - enum: 16a5b5b45fSManish Narani - xlnx,zynqmp-dwc3 17a5b5b45fSManish Narani - xlnx,versal-dwc3 18a5b5b45fSManish Narani reg: 19a5b5b45fSManish Narani maxItems: 1 20a5b5b45fSManish Narani 21a5b5b45fSManish Narani "#address-cells": 22a5b5b45fSManish Narani enum: [ 1, 2 ] 23a5b5b45fSManish Narani 24a5b5b45fSManish Narani "#size-cells": 25a5b5b45fSManish Narani enum: [ 1, 2 ] 26a5b5b45fSManish Narani 27a5b5b45fSManish Narani ranges: true 28a5b5b45fSManish Narani 29a5b5b45fSManish Narani power-domains: 30a5b5b45fSManish Narani description: specifies a phandle to PM domain provider node 31a5b5b45fSManish Narani maxItems: 1 32a5b5b45fSManish Narani 33a5b5b45fSManish Narani clocks: 34a5b5b45fSManish Narani description: 35a5b5b45fSManish Narani A list of phandle and clock-specifier pairs for the clocks 36a5b5b45fSManish Narani listed in clock-names. 37a5b5b45fSManish Narani items: 38a5b5b45fSManish Narani - description: Master/Core clock, has to be >= 125 MHz 39a5b5b45fSManish Narani for SS operation and >= 60MHz for HS operation. 40a5b5b45fSManish Narani - description: Clock source to core during PHY power down. 41a5b5b45fSManish Narani 42a5b5b45fSManish Narani clock-names: 43a5b5b45fSManish Narani items: 44a5b5b45fSManish Narani - const: bus_clk 45a5b5b45fSManish Narani - const: ref_clk 46a5b5b45fSManish Narani 47a5b5b45fSManish Narani resets: 48a5b5b45fSManish Narani description: 49a5b5b45fSManish Narani A list of phandles for resets listed in reset-names. 50a5b5b45fSManish Narani 51a5b5b45fSManish Narani items: 52a5b5b45fSManish Narani - description: USB core reset 53a5b5b45fSManish Narani - description: USB hibernation reset 54a5b5b45fSManish Narani - description: USB APB reset 55a5b5b45fSManish Narani 56a5b5b45fSManish Narani reset-names: 57a5b5b45fSManish Narani items: 58a5b5b45fSManish Narani - const: usb_crst 59a5b5b45fSManish Narani - const: usb_hibrst 60a5b5b45fSManish Narani - const: usb_apbrst 61a5b5b45fSManish Narani 62a5b5b45fSManish Narani phys: 63a5b5b45fSManish Narani minItems: 1 64a5b5b45fSManish Narani maxItems: 2 65a5b5b45fSManish Narani 66a5b5b45fSManish Narani phy-names: 67a5b5b45fSManish Narani minItems: 1 68a5b5b45fSManish Narani maxItems: 2 69a5b5b45fSManish Narani items: 70a5b5b45fSManish Narani enum: 71a5b5b45fSManish Narani - usb2-phy 72a5b5b45fSManish Narani - usb3-phy 73a5b5b45fSManish Narani 741cda12b1SPiyush Mehta reset-gpios: 751cda12b1SPiyush Mehta description: GPIO used for the reset ulpi-phy 761cda12b1SPiyush Mehta maxItems: 1 771cda12b1SPiyush Mehta 78a5b5b45fSManish Narani# Required child node: 79a5b5b45fSManish Narani 80a5b5b45fSManish NaranipatternProperties: 81a5b5b45fSManish Narani "^usb@[0-9a-f]+$": 82a5b5b45fSManish Narani $ref: snps,dwc3.yaml# 83a5b5b45fSManish Narani 84a5b5b45fSManish Naranirequired: 85a5b5b45fSManish Narani - compatible 86a5b5b45fSManish Narani - reg 87a5b5b45fSManish Narani - "#address-cells" 88a5b5b45fSManish Narani - "#size-cells" 89a5b5b45fSManish Narani - ranges 90a5b5b45fSManish Narani - power-domains 91a5b5b45fSManish Narani - clocks 92a5b5b45fSManish Narani - clock-names 93a5b5b45fSManish Narani - resets 94a5b5b45fSManish Narani - reset-names 95a5b5b45fSManish Narani 96a5b5b45fSManish NaraniadditionalProperties: false 97a5b5b45fSManish Narani 98a5b5b45fSManish Naraniexamples: 99a5b5b45fSManish Narani - | 100a5b5b45fSManish Narani #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 101a5b5b45fSManish Narani #include <dt-bindings/power/xlnx-zynqmp-power.h> 102a5b5b45fSManish Narani #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 103a5b5b45fSManish Narani #include <dt-bindings/clock/xlnx-zynqmp-clk.h> 104a5b5b45fSManish Narani #include <dt-bindings/reset/xlnx-zynqmp-resets.h> 105a5b5b45fSManish Narani #include <dt-bindings/phy/phy.h> 106a5b5b45fSManish Narani axi { 107a5b5b45fSManish Narani #address-cells = <2>; 108a5b5b45fSManish Narani #size-cells = <2>; 109a5b5b45fSManish Narani 110a5b5b45fSManish Narani usb@0 { 111a5b5b45fSManish Narani #address-cells = <0x2>; 112a5b5b45fSManish Narani #size-cells = <0x2>; 113a5b5b45fSManish Narani compatible = "xlnx,zynqmp-dwc3"; 114a5b5b45fSManish Narani reg = <0x0 0xff9d0000 0x0 0x100>; 115a5b5b45fSManish Narani clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; 116a5b5b45fSManish Narani clock-names = "bus_clk", "ref_clk"; 117a5b5b45fSManish Narani power-domains = <&zynqmp_firmware PD_USB_0>; 118a5b5b45fSManish Narani resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 119a5b5b45fSManish Narani <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 120a5b5b45fSManish Narani <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 121a5b5b45fSManish Narani reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 122a5b5b45fSManish Narani phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 123a5b5b45fSManish Narani phy-names = "usb3-phy"; 124a5b5b45fSManish Narani ranges; 125a5b5b45fSManish Narani 126a5b5b45fSManish Narani usb@fe200000 { 127a5b5b45fSManish Narani compatible = "snps,dwc3"; 128a5b5b45fSManish Narani reg = <0x0 0xfe200000 0x0 0x40000>; 129a5b5b45fSManish Narani interrupt-names = "host", "otg"; 130a5b5b45fSManish Narani interrupts = <0 65 4>, <0 69 4>; 131a5b5b45fSManish Narani dr_mode = "host"; 132a5b5b45fSManish Narani dma-coherent; 133a5b5b45fSManish Narani }; 134a5b5b45fSManish Narani }; 135a5b5b45fSManish Narani }; 136