Lines Matching +full:zynqmp +full:- +full:clk

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
15 - enum:
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
21 "#address-cells":
24 "#size-cells":
29 power-domains:
35 A list of phandle and clock-specifier pairs for the clocks
36 listed in clock-names.
38 - description: Master/Core clock, has to be >= 125 MHz
40 - description: Clock source to core during PHY power down.
42 clock-names:
44 - const: bus_clk
45 - const: ref_clk
49 A list of phandles for resets listed in reset-names.
52 - description: USB core reset
53 - description: USB hibernation reset
54 - description: USB APB reset
56 reset-names:
58 - const: usb_crst
59 - const: usb_hibrst
60 - const: usb_apbrst
66 phy-names:
71 - usb2-phy
72 - usb3-phy
74 reset-gpios:
75 description: GPIO used for the reset ulpi-phy
81 "^usb@[0-9a-f]+$":
85 - compatible
86 - reg
87 - "#address-cells"
88 - "#size-cells"
89 - ranges
90 - power-domains
91 - clocks
92 - clock-names
93 - resets
94 - reset-names
99 - |
100 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
101 #include <dt-bindings/power/xlnx-zynqmp-power.h>
102 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
103 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
104 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
105 #include <dt-bindings/phy/phy.h>
107 #address-cells = <2>;
108 #size-cells = <2>;
111 #address-cells = <0x2>;
112 #size-cells = <0x2>;
113 compatible = "xlnx,zynqmp-dwc3";
116 clock-names = "bus_clk", "ref_clk";
117 power-domains = <&zynqmp_firmware PD_USB_0>;
121 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
123 phy-names = "usb3-phy";
129 interrupt-names = "host", "otg";
132 dma-coherent;