1*3fde0e16SJolly Shah# SPDX-License-Identifier: GPL-2.0 2*3fde0e16SJolly Shah# Zynq Ultrascale+ MPSoC clock specific Makefile 3*3fde0e16SJolly Shah 4*3fde0e16SJolly Shahobj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o 5