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/openbmc/u-boot/doc/
H A DREADME.zynq1 # SPDX-License-Identifier: GPL-2.0+
3 # Xilinx ZYNQ U-Boot
7 1. About this
9 This document describes the information about Xilinx Zynq U-Boot -
12 2. Zynq boards
14 Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
18 * zc702 (single qspi, gem0, mmc) [1]
19 * zc706 (dual parallel qspi, gem0, mmc) [2]
20 * zed (single qspi, gem0, mmc) [3]
21 * microzed (single qspi, gem0, mmc) [4]
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/openbmc/u-boot/arch/arm/dts/
H A Dzynq-cse-qspi.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx CSE QSPI board DTS
5 * Copyright (C) 2015 - 2017 Xilinx, Inc.
7 /dts-v1/;
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Zynq CSE QSPI Board";
13 compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
16 spi0 = &qspi;
26 stdout-path = "serial0:115200n8";
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H A Dzynq-topic-miami.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2016 Topic Embedded Products
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
11 model = "Topic Miami Zynq Board";
12 compatible = "topic,miami", "xlnx,zynq-7000";
16 spi0 = &qspi;
29 stdout-path = "serial0:115200n8";
33 &qspi {
34 u-boot,dm-pre-reloc;
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H A Dzynq-cc108.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2018 Xilinx, Inc.
6 * (C) Copyright 2007-2013 Michal Simek
7 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
11 /dts-v1/;
12 /include/ "zynq-7000.dtsi"
16 compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
21 spi0 = &qspi;
26 stdout-path = "serial0:115200n8";
35 compatible = "usb-nop-xceiv";
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H A Dzynq-zed.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 - 2015 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
16 spi0 = &qspi;
27 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
37 ps-clk-frequency = <33333333>;
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H A Dzynq-dlc20-rev1.0.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
11 model = "Zynq DLC20 Rev1.0";
12 compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20",
13 "xlnx,zynq-7000";
19 spi0 = &qspi;
30 stdout-path = "serial0:115200n8";
34 compatible = "ulpi-phy";
35 #phy-cells = <0>;
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H A Dzynq-zybo.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 - 2015 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
16 spi0 = &qspi;
27 stdout-path = "serial0:115200n8";
31 #phy-cells = <0>;
32 compatible = "usb-nop-xceiv";
33 reset-gpios = <&gpio0 46 1>;
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H A Dzynq-zc770-xm010.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
18 spi0 = &qspi;
24 stdout-path = "serial0:115200n8";
33 compatible = "usb-nop-xceiv";
34 #phy-cells = <0>;
44 phy-mode = "rgmii-id";
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H A Dzynq-minized.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
7 * Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
10 /dts-v1/;
11 #include "zynq-7000.dtsi"
14 model = "Avnet Zynq MiniZed Development Board";
15 compatible = "avnet,minized", "xlnx,zynq-7000";
20 spi0 = &qspi;
31 stdout-path = "serial0:115200n8";
35 compatible = "usb-nop-xceiv";
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H A Dzynq-topic-miamilite.dts1 // SPDX-License-Identifier: GPL-2.0+
7 #include "zynq-topic-miami.dts"
10 model = "Topic Miami Lite Zynq Board";
11 compatible = "topic,miamilite", "xlnx,zynq-7000";
14 &qspi {
15 is-dual = <1>;
H A Dzynq-topic-miamiplus.dts1 // SPDX-License-Identifier: GPL-2.0+
7 #include "zynq-topic-miami.dts"
10 model = "Topic Miami+ Zynq Board";
11 compatible = "topic,miamiplus", "xlnx,zynq-7000";
14 /* The miamiplus contains a speedgrade-2 device and runs at 800MHz */
16 operating-points = <
23 &qspi {
24 is-dual = <1>;
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "xlnx,zynq-7000";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0+
3 dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb
4 dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
5 dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
6 dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
8 dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
9 dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
10 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
11 exynos4210-smdkv310.dtb \
12 exynos4210-universal_c210.dtb \
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 - 2015 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
17 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
32 compatible = "usb-nop-xceiv";
33 #phy-cells = <0>;
38 ps-clk-frequency = <33333333>;
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dxlnx,zynq-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
14 - $ref: spi-controller.yaml#
17 - Michal Simek <michal.simek@amd.com>
22 const: xlnx,zynq-qspi-1.0
25 maxItems: 1
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H A Dspi-zynqmp-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - xlnx,versal-qspi-1.0
19 - xlnx,zynqmp-qspi-1.0
25 maxItems: 1
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/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-zynq-qspi.txt1 Xilinx Zynq QSPI controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible : Should be "xlnx,zynq-qspi-1.0".
6 - reg : Physical base address and size of QSPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - interrupt-parent : Must be core interrupt controller
10 - clock-names : List of input clock names - "ref_clk", "pclk"
12 - clocks : Clock phandles (see clock bindings for details).
15 - num-cs : Number of chip selects used.
18 qspi@e000d000 {
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/openbmc/u-boot/drivers/spi/
H A DKconfig16 typically use driver-private data instead of extending the
24 by providing an high-level interface to send memory-like commands.
65 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
94 Enable the Broadcom set-top box SPI driver. This driver can
99 bool "Cadence QSPI driver"
101 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
158 bool "Mediatek QSPI driver"
161 Enable the Mediatek QSPI driver. This driver can be
163 Mediatek QSPI IP core.
178 to access the SPI NOR flash, MMC-over-SPI on platforms based on
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H A Dzynq_qspi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
17 /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
26 #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
32 #define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
34 /* zynq qspi Transmit Data Register */
35 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
36 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
37 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
38 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
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/openbmc/qemu/hw/arm/
H A Dxilinx_zynq.c2 * Xilinx Zynq Baseboard System emulation.
28 #include "hw/adc/zynq-xadc.h"
31 #include "qemu/error-report.h"
36 #include "hw/qdev-clock.h"
41 #include "target/arm/cpu-qom.h"
44 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
112 rom_add_blob_fixed("board-setup", board_setup_blob, in zynq_write_board_setup()
125 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); in gem_init()
141 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; in zynq_init_spi_flashes()
144 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); in zynq_init_spi_flashes()
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/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
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/openbmc/linux/drivers/spi/
H A Dspi-zynq-qspi.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
41 * QSPI Configuration Register bit Masks
44 * of the QSPI controller
52 #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */
57 * QSPI Configuration Register - Baud rate and slave select
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/openbmc/u-boot/include/configs/
H A Dtopic_miami.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Configuration for Zynq Evaluation and Development Board - Miami
6 * See zynq-common.h for Zynq common configs
15 #include "zynq-common.h"
29 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
57 "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
58 "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
105 "qspiboot=echo Booting from QSPI flash... && " \
109 "bootm ${kernel_addr} - ${devicetree_addr}\0" \
116 "bootm ${kernel_addr} - ${devicetree_addr}; " \
H A Dzynq-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * (C) Copyright 2013 - 2018 Xilinx, Inc.
6 * Common configuration options for all Zynq boards.
44 /* QSPI */
50 # define CONFIG_SYS_MAX_FLASH_BANKS 1
59 #define CONFIG_SYS_MAX_NAND_DEVICE 1
83 "${kernel_image} fat 0 1\\\\;" \
84 "${devicetree_image} fat 0 1\\\\;" \
85 "${ramdisk_image} fat 0 1\0" \
140 # define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
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/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
[all …]

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