Lines Matching +full:zynq +full:- +full:qspi +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "xlnx,zynq-7000";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
24 cpu0-supply = <®ulator_vccpint>;
25 operating-points = <
32 cpu1: cpu@1 {
33 compatible = "arm,cortex-a9";
35 reg = <1>;
40 fpga_full: fpga-full {
41 compatible = "fpga-region";
42 fpga-mgr = <&devcfg>;
43 #address-cells = <1>;
44 #size-cells = <1>;
49 compatible = "arm,cortex-a9-pmu";
51 interrupt-parent = <&intc>;
57 compatible = "regulator-fixed";
58 regulator-name = "VCCPINT";
59 regulator-min-microvolt = <1000000>;
60 regulator-max-microvolt = <1000000>;
61 regulator-boot-on;
62 regulator-always-on;
66 u-boot,dm-pre-reloc;
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 interrupt-parent = <&intc>;
74 compatible = "xlnx,zynq-xadc-1.00.a";
77 interrupt-parent = <&intc>;
82 compatible = "xlnx,zynq-can-1.0";
85 clock-names = "can_clk", "pclk";
88 interrupt-parent = <&intc>;
89 tx-fifo-depth = <0x40>;
90 rx-fifo-depth = <0x40>;
94 compatible = "xlnx,zynq-can-1.0";
97 clock-names = "can_clk", "pclk";
100 interrupt-parent = <&intc>;
101 tx-fifo-depth = <0x40>;
102 rx-fifo-depth = <0x40>;
106 compatible = "xlnx,zynq-gpio-1.0";
107 #gpio-cells = <2>;
109 gpio-controller;
110 interrupt-controller;
111 #interrupt-cells = <2>;
112 interrupt-parent = <&intc>;
118 compatible = "cdns,i2c-r1p10";
121 interrupt-parent = <&intc>;
124 #address-cells = <1>;
125 #size-cells = <0>;
129 compatible = "cdns,i2c-r1p10";
132 interrupt-parent = <&intc>;
135 #address-cells = <1>;
136 #size-cells = <0>;
139 intc: interrupt-controller@f8f01000 {
140 compatible = "arm,cortex-a9-gic";
141 #interrupt-cells = <3>;
142 interrupt-controller;
147 L2: cache-controller@f8f02000 {
148 compatible = "arm,pl310-cache";
151 arm,data-latency = <3 2 2>;
152 arm,tag-latency = <2 2 2>;
153 cache-unified;
154 cache-level = <2>;
157 mc: memory-controller@f8006000 {
158 compatible = "xlnx,zynq-ddrc-a05";
163 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
166 clock-names = "uart_clk", "pclk";
172 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
175 clock-names = "uart_clk", "pclk";
181 compatible = "xlnx,zynq-spi-r1p6";
184 interrupt-parent = <&intc>;
187 clock-names = "ref_clk", "pclk";
188 #address-cells = <1>;
189 #size-cells = <0>;
193 compatible = "xlnx,zynq-spi-r1p6";
196 interrupt-parent = <&intc>;
199 clock-names = "ref_clk", "pclk";
200 #address-cells = <1>;
201 #size-cells = <0>;
204 qspi: spi@e000d000 { label
205 clock-names = "ref_clk", "pclk";
207 compatible = "xlnx,zynq-qspi-1.0";
209 interrupt-parent = <&intc>;
212 #address-cells = <1>;
213 #size-cells = <0>;
217 compatible = "cdns,zynq-gem", "cdns,gem";
222 clock-names = "pclk", "hclk", "tx_clk";
223 #address-cells = <1>;
224 #size-cells = <0>;
228 compatible = "cdns,zynq-gem", "cdns,gem";
233 clock-names = "pclk", "hclk", "tx_clk";
234 #address-cells = <1>;
235 #size-cells = <0>;
239 compatible = "arasan,sdhci-8.9a";
241 clock-names = "clk_xin", "clk_ahb";
243 interrupt-parent = <&intc>;
249 compatible = "arasan,sdhci-8.9a";
251 clock-names = "clk_xin", "clk_ahb";
253 interrupt-parent = <&intc>;
259 u-boot,dm-pre-reloc;
260 #address-cells = <1>;
261 #size-cells = <1>;
262 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
266 u-boot,dm-pre-reloc;
267 #clock-cells = <1>;
268 compatible = "xlnx,ps7-clkc";
269 fclk-enable = <0>;
270 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
285 compatible = "xlnx,zynq-reset";
287 #reset-cells = <1>;
292 compatible = "xlnx,pinctrl-zynq";
301 interrupt-parent = <&intc>;
302 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
309 #dma-cells = <1>;
310 #dma-channels = <8>;
311 #dma-requests = <4>;
313 clock-names = "apb_pclk";
317 compatible = "xlnx,zynq-devcfg-1.0";
318 interrupt-parent = <&intc>;
322 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
327 compatible = "xlnx,zynq-efuse";
332 compatible = "arm,cortex-a9-global-timer";
334 interrupts = <1 11 0x301>;
335 interrupt-parent = <&intc>;
340 interrupt-parent = <&intc>;
348 interrupt-parent = <&intc>;
356 interrupt-parent = <&intc>;
357 interrupts = <1 13 0x301>;
358 compatible = "arm,cortex-a9-twd-timer";
364 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
367 interrupt-parent = <&intc>;
374 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
377 interrupt-parent = <&intc>;
385 compatible = "cdns,wdt-r1p2";
386 interrupt-parent = <&intc>;
387 interrupts = <0 9 1>;
389 timeout-sec = <10>;