Lines Matching +full:zynq +full:- +full:qspi +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx CSE QSPI board DTS
5 * Copyright (C) 2015 - 2017 Xilinx, Inc.
7 /dts-v1/;
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Zynq CSE QSPI Board";
13 compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
16 spi0 = &qspi;
26 stdout-path = "serial0:115200n8";
32 u-boot,dm-pre-reloc;
36 u-boot,dm-pre-reloc;
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 interrupt-parent = <&intc>;
43 intc: interrupt-controller@f8f01000 {
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
46 interrupt-controller;
51 qspi: spi@e000d000 { label
52 clock-names = "ref_clk", "pclk";
54 compatible = "xlnx,zynq-qspi-1.0";
56 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 num-cs = <1>;
65 spi-tx-bus-width = <1>;
66 spi-rx-bus-width = <4>;
67 spi-max-frequency = <50000000>;
68 #address-cells = <1>;
69 #size-cells = <1>;
70 partition@qspi-fsbl-uboot {
71 label = "qspi-fsbl-uboot";
74 partition@qspi-linux {
75 label = "qspi-linux";
78 partition@qspi-device-tree {
79 label = "qspi-device-tree";
82 partition@qspi-rootfs {
83 label = "qspi-rootfs";
86 partition@qspi-bitstream {
87 label = "qspi-bitstream";
94 u-boot,dm-pre-reloc;
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
101 #clock-cells = <1>;
102 compatible = "xlnx,ps7-clkc";
103 fclk-enable = <0xf>;
104 u-boot,dm-pre-reloc;
105 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",