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/openbmc/linux/drivers/net/ethernet/xilinx/
H A DKconfig3 # Xilinx device configuration
7 bool "Xilinx devices"
14 the questions about Xilinx devices. If you say Y, you will be asked
20 tristate "Xilinx 10/100 Ethernet Lite support"
24 This driver supports the 10/100 Ethernet Lite from Xilinx.
27 tristate "Xilinx 10/100/1000 AXI Ethernet support"
31 This driver supports the 10/100/1000 Ethernet from Xilinx for the
32 AXI bus interface used in Xilinx Virtex FPGAs and Soc's.
35 tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
39 This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
[all …]
/openbmc/linux/Documentation/devicetree/bindings/
H A Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
89 That covers the general approach to binding xilinx IP cores into the
92 i) Xilinx ML300 Framebuffer
105 ii) Xilinx SystemACE
107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
114 iii) Xilinx EMAC and Xilinx TEMAC
116 Xilinx Ethernet devices. In addition to general xilinx properties
121 iv) Xilinx Uartlite
[all …]
/openbmc/linux/drivers/media/platform/xilinx/
H A DKconfig3 comment "Xilinx media platform drivers"
6 tristate "Xilinx Video IP (EXPERIMENTAL)"
14 Driver for Xilinx Video IP Pipelines
18 tristate "Xilinx CSI-2 Rx Subsystem"
20 Driver for Xilinx MIPI CSI-2 Rx Subsystem. This is a V4L sub-device
25 tristate "Xilinx Video Test Pattern Generator"
29 Driver for the Xilinx Video Test Pattern Generator
32 tristate "Xilinx Video Timing Controller"
35 Driver for the Xilinx Video Timing Controller
H A DMakefile3 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
5 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
6 obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
7 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
8 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dxilinx.yaml4 $id: http://devicetree.org/schemas/arm/xilinx.yaml#
7 title: Xilinx Zynq Platforms
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
52 - description: Xilinx internal board zc1232
58 - description: Xilinx internal board zc1254
64 - description: Xilinx evaluation board zcu1275
70 - description: Xilinx 96boards compatible board zcu100
76 - description: Xilinx 96boards compatible board Ultra96
84 - description: Xilinx evaluation board zcu102
94 - description: Xilinx evaluation board zcu104
[all …]
/openbmc/qemu/contrib/gitdm/
H A Dgroup-map-amd1 # AMD acquired Xilinx and contributors have been slowly updating emails
3 edgar.iglesias@xilinx.com
4 fnu.vikram@xilinx.com
5 francisco.iglesias@xilinx.com
6 sai.pavan.boddu@xilinx.com
7 stefano.stabellini@xilinx.com
8 tong.ho@xilinx.com
/openbmc/linux/sound/soc/xilinx/
H A DKconfig3 tristate "Audio support for the Xilinx I2S"
5 Select this option to enable Xilinx I2S Audio. This enables
6 I2S playback and capture using xilinx soft IP. In transmitter
12 tristate "Audio support for the Xilinx audio formatter"
14 Select this option to enable Xilinx audio formatter
19 tristate "Audio support for the Xilinx SPDIF"
21 Select this option to enable Xilinx SPDIF Audio.
/openbmc/u-boot/doc/
H A DREADME.zynq3 # Xilinx ZYNQ U-Boot
5 # (C) Copyright 2013 Xilinx, Inc.
9 This document describes the information about Xilinx Zynq U-Boot -
14 Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
75 [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
76 [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
79 [5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
82 Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
/openbmc/linux/drivers/irqchip/
H A Dirq-xilinx-intc.c3 * Copyright (C) 2012-2013 Xilinx, Inc.
69 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); in intc_enable_or_unmask()
85 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); in intc_disable_or_mask()
93 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); in intc_ack()
102 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); in intc_mask_ack()
108 .name = "Xilinx INTC",
182 pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); in xilinx_intc_of_init()
188 pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n"); in xilinx_intc_of_init()
193 pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); in xilinx_intc_of_init()
195 pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n", in xilinx_intc_of_init()
[all …]
/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp4 Contact: "Jolly Shah" <jollys@xilinx.com>
13 other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}.
25 Users: Xilinx
30 Contact: "Jolly Shah" <jollys@xilinx.com>
40 Four registers are used by the FSBL and other Xilinx
54 Users: Xilinx
59 Contact: "Jolly Shah" <jollys@xilinx.com>
91 Users: Xilinx
96 Contact: "Jolly Shah" <jollys@xilinx.com>
115 Users: Xilinx
[all …]
/openbmc/u-boot/drivers/fpga/
H A DKconfig46 bool "Enable Xilinx FPGA drivers"
49 Enable Xilinx FPGA specific functions which includes bitstream
53 bool "Enable Xilinx FPGA driver for ZynqMP"
57 on Xilinx Zynq UltraScale+ (ZynqMP) device.
65 bool "Enable Xilinx FPGA for Zynq"
69 on Xilinx Zynq devices.
/openbmc/linux/drivers/fpga/
H A DKconfig56 tristate "Xilinx Zynq FPGA"
59 FPGA manager driver support for Xilinx Zynq FPGAs.
68 tristate "Xilinx Configuration over Slave Serial (SPI)"
71 FPGA manager driver support for Xilinx FPGA configuration
117 tristate "Xilinx LogiCORE PR Decoupler"
121 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
122 or Xilinx Dynamic Function eXchange AIX Shutdown Manager.
229 tristate "Xilinx ZynqMP FPGA"
232 FPGA manager driver support for Xilinx ZynqMP FPGAs.
238 tristate "Xilinx Versal FPGA"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt1 Xilinx XADC device driver
3 This binding document describes the bindings for the Xilinx 7 Series XADC as well
6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
14 The Xilinx System Monitor is an ADC that is found in the UltraScale and
15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
16 communication. Xilinx provides a standard IP core that can be used to access the
18 called the Xilinx System Management Wizard. This document describes the bindings
28 Xilinx System Management Wizard fabric IP core to access the
/openbmc/linux/drivers/net/ethernet/sfc/
H A Def100.c5 * Copyright 2019-2022 Xilinx Inc.
32 /* Expected size of a Xilinx continuation address table entry. */
86 "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n", in ef100_pci_parse_ef100_entry()
104 /* Parse a Xilinx capabilities table entry describing a continuation to a new
128 "Bad BAR value of %d in Xilinx capabilities sub-table.\n", in ef100_pci_parse_continue_entry()
138 "Xilinx table will overrun BAR[%d] offset=0x%llx\n", in ef100_pci_parse_continue_entry()
149 "Mapping new BAR for Xilinx table failed, rc=%d\n", rc); in ef100_pci_parse_continue_entry()
175 /* Iterate over the Xilinx capabilities table in the currently mapped BAR and
197 "Seen Xilinx table entry 0x%x size 0x%x at 0x%llx in BAR[%d]\n", in ef100_pci_walk_xilinx_table()
202 "Xilinx table entry too short len=0x%x\n", entry_size); in ef100_pci_walk_xilinx_table()
[all …]
/openbmc/linux/drivers/char/xilinx_hwicap/
H A Dfifo_icap.h3 * Author: Xilinx, Inc.
10 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
12 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
14 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
17 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
24 * (c) Copyright 2007-2008 Xilinx Inc.
H A Dbuffer_icap.h3 * Author: Xilinx, Inc.
10 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
12 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
14 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
17 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
24 * (c) Copyright 2003-2008 Xilinx Inc.
/openbmc/u-boot/board/xilinx/
H A DKconfig20 generate custom files using the Xilinx development tools.
30 board/xilinx/zynq/$(CONFIG_DEFAULT_DEVICE_TREE)/ps7_init_gpl.c
32 board/xilinx/zynqmp/$(CONFIG_DEFAULT_DEVICE_TREE)/psu_init_gpl.c
36 board/xilinx/zynq/ps7_init_gpl.c for Zynq-7000, or
37 board/xilinx/zynqmp/psu_init_gpl.c for ZynqMP. This file
/openbmc/openbmc/meta-arm/meta-arm/recipes-bsp/trusted-firmware-a/files/
H A D0001-fix-zynqmp-handle-secure-SGI-at-EL1-for-OP-TEE.patch13 plat/xilinx/zynqmp/platform.mk | 2 +-
18 diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
20 --- a/plat/xilinx/zynqmp/platform.mk
21 +++ b/plat/xilinx/zynqmp/platform.mk
/openbmc/u-boot/include/configs/
H A Dxilinx_zynqmp_mini_emmc.h3 * Configuration for Xilinx ZynqMP eMMC Flash utility
5 * (C) Copyright 2018 Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
7 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
H A Dxilinx_zynqmp_mini_qspi.h3 * Configuration for Xilinx ZynqMP QSPI Flash utility
5 * (C) Copyright 2018 Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
7 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
H A Dxilinx_versal_mini_qspi.h3 * Configuration for Xilinx Versal QSPI Flash utility
5 * (C) Copyright 2018-2019 Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
7 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
H A Dxilinx_zynqmp_mini_nand.h3 * Configuration for Xilinx ZynqMP Nand Flash utility
5 * (C) Copyright 2018 Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
7 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
/openbmc/linux/drivers/staging/axis-fifo/
H A DKconfig3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
/openbmc/u-boot/arch/arm/dts/
H A Dversal-mini-emmc1.dts3 * dts file for Xilinx Versal Mini eMMC1 Configuration
5 * (C) Copyright 2018-2019, Xilinx, Inc.
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
17 model = "Xilinx Versal MINI eMMC1";
H A Dversal-mini-emmc0.dts3 * dts file for Xilinx Versal Mini eMMC0 Configuration
5 * (C) Copyright 2018-2019, Xilinx, Inc.
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
17 model = "Xilinx Versal MINI eMMC0";

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