1*14ed50a4SSiva Durga Prasad Paladugu /* SPDX-License-Identifier: GPL-2.0+ */ 2*14ed50a4SSiva Durga Prasad Paladugu /* 3*14ed50a4SSiva Durga Prasad Paladugu * Configuration for Xilinx ZynqMP QSPI Flash utility 4*14ed50a4SSiva Durga Prasad Paladugu * 5*14ed50a4SSiva Durga Prasad Paladugu * (C) Copyright 2018 Xilinx, Inc. 6*14ed50a4SSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 7*14ed50a4SSiva Durga Prasad Paladugu * Siva Durga Prasad Paladugu <sivadur@xilinx.com> 8*14ed50a4SSiva Durga Prasad Paladugu */ 9*14ed50a4SSiva Durga Prasad Paladugu 10*14ed50a4SSiva Durga Prasad Paladugu #ifndef __CONFIG_ZYNQMP_MINI_QSPI_H 11*14ed50a4SSiva Durga Prasad Paladugu #define __CONFIG_ZYNQMP_MINI_QSPI_H 12*14ed50a4SSiva Durga Prasad Paladugu 13*14ed50a4SSiva Durga Prasad Paladugu #include <configs/xilinx_zynqmp_mini.h> 14*14ed50a4SSiva Durga Prasad Paladugu 15*14ed50a4SSiva Durga Prasad Paladugu #define CONFIG_SYS_ICACHE_OFF 16*14ed50a4SSiva Durga Prasad Paladugu #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) 17*14ed50a4SSiva Durga Prasad Paladugu #define CONFIG_SYS_MALLOC_LEN 0x2000 18*14ed50a4SSiva Durga Prasad Paladugu 19*14ed50a4SSiva Durga Prasad Paladugu #endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ 20