xref: /openbmc/linux/drivers/fpga/Kconfig (revision 3969f645)
1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only
26a8c3be7SAlan Tull#
36a8c3be7SAlan Tull# FPGA framework configuration
46a8c3be7SAlan Tull#
56a8c3be7SAlan Tull
650fa0285SVincent Legollmenuconfig FPGA
76a8c3be7SAlan Tull	tristate "FPGA Configuration Framework"
86a8c3be7SAlan Tull	help
96a8c3be7SAlan Tull	  Say Y here if you want support for configuring FPGAs from the
10df82d2ecSTom Rix	  kernel.  The FPGA framework adds an FPGA manager class and FPGA
116a8c3be7SAlan Tull	  manager drivers.
126a8c3be7SAlan Tull
13fab6266eSAlan Tullif FPGA
14fab6266eSAlan Tull
15fab6266eSAlan Tullconfig FPGA_MGR_SOCFPGA
16fab6266eSAlan Tull	tristate "Altera SOCFPGA FPGA Manager"
173a1fef70SKrzysztof Kozlowski	depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
18fab6266eSAlan Tull	help
19fab6266eSAlan Tull	  FPGA manager driver support for Altera SOCFPGA.
20fab6266eSAlan Tull
21acbb910aSAlan Tullconfig FPGA_MGR_SOCFPGA_A10
22acbb910aSAlan Tull	tristate "Altera SoCFPGA Arria10"
233a1fef70SKrzysztof Kozlowski	depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
24a0e1b618SJason Gunthorpe	select REGMAP_MMIO
25acbb910aSAlan Tull	help
26acbb910aSAlan Tull	  FPGA manager driver support for Altera Arria10 SoCFPGA.
27acbb910aSAlan Tull
2884e93f1dSAlan Tullconfig ALTERA_PR_IP_CORE
2984e93f1dSAlan Tull	tristate "Altera Partial Reconfiguration IP Core"
304348f7e2SFlorian Fainelli	help
3184e93f1dSAlan Tull	  Core driver support for Altera Partial Reconfiguration IP component
3284e93f1dSAlan Tull
3384e93f1dSAlan Tullconfig ALTERA_PR_IP_CORE_PLAT
3484e93f1dSAlan Tull	tristate "Platform support of Altera Partial Reconfiguration IP Core"
3584e93f1dSAlan Tull	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
3684e93f1dSAlan Tull	help
3784e93f1dSAlan Tull	  Platform driver support for Altera Partial Reconfiguration IP
3884e93f1dSAlan Tull	  component
3984e93f1dSAlan Tull
4084e93f1dSAlan Tullconfig FPGA_MGR_ALTERA_PS_SPI
4184e93f1dSAlan Tull	tristate "Altera FPGA Passive Serial over SPI"
4284e93f1dSAlan Tull	depends on SPI
433d139703SYueHaibing	select BITREVERSE
4484e93f1dSAlan Tull	help
4584e93f1dSAlan Tull	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
4684e93f1dSAlan Tull	  using the passive serial interface over SPI.
4784e93f1dSAlan Tull
4884e93f1dSAlan Tullconfig FPGA_MGR_ALTERA_CVP
49e5891517SThor Thayer	tristate "Altera CvP FPGA Manager"
5084e93f1dSAlan Tull	depends on PCI
5184e93f1dSAlan Tull	help
52e5891517SThor Thayer	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
53e5891517SThor Thayer	  Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
5484e93f1dSAlan Tull
5584e93f1dSAlan Tullconfig FPGA_MGR_ZYNQ_FPGA
5684e93f1dSAlan Tull	tristate "Xilinx Zynq FPGA"
5784e93f1dSAlan Tull	depends on ARCH_ZYNQ || COMPILE_TEST
5884e93f1dSAlan Tull	help
5984e93f1dSAlan Tull	  FPGA manager driver support for Xilinx Zynq FPGAs.
604348f7e2SFlorian Fainelli
61e7eef1d7SAlan Tullconfig FPGA_MGR_STRATIX10_SOC
62e7eef1d7SAlan Tull	tristate "Intel Stratix10 SoC FPGA Manager"
634a9a1a56SKrzysztof Kozlowski	depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
64e7eef1d7SAlan Tull	help
65e7eef1d7SAlan Tull	  FPGA manager driver support for the Intel Stratix10 SoC.
66e7eef1d7SAlan Tull
67061c97d1SAnatolij Gustschinconfig FPGA_MGR_XILINX_SPI
68061c97d1SAnatolij Gustschin	tristate "Xilinx Configuration over Slave Serial (SPI)"
69061c97d1SAnatolij Gustschin	depends on SPI
70061c97d1SAnatolij Gustschin	help
71061c97d1SAnatolij Gustschin	  FPGA manager driver support for Xilinx FPGA configuration
72061c97d1SAnatolij Gustschin	  over slave serial interface.
73061c97d1SAnatolij Gustschin
7484e93f1dSAlan Tullconfig FPGA_MGR_ICE40_SPI
7584e93f1dSAlan Tull	tristate "Lattice iCE40 SPI"
7684e93f1dSAlan Tull	depends on OF && SPI
7737784706SMoritz Fischer	help
7884e93f1dSAlan Tull	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
7984e93f1dSAlan Tull
8088fb3a00SPaolo Pisaticonfig FPGA_MGR_MACHXO2_SPI
8188fb3a00SPaolo Pisati	tristate "Lattice MachXO2 SPI"
8288fb3a00SPaolo Pisati	depends on SPI
8388fb3a00SPaolo Pisati	help
8488fb3a00SPaolo Pisati	  FPGA manager driver support for Lattice MachXO2 configuration
8588fb3a00SPaolo Pisati	  over slave SPI interface.
8688fb3a00SPaolo Pisati
8784e93f1dSAlan Tullconfig FPGA_MGR_TS73XX
8884e93f1dSAlan Tull	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
8984e93f1dSAlan Tull	depends on ARCH_EP93XX && MACH_TS72XX
9084e93f1dSAlan Tull	help
9184e93f1dSAlan Tull	  FPGA manager driver support for the Altera Cyclone II FPGA
9284e93f1dSAlan Tull	  present on the TS-73xx SBC boards.
9337784706SMoritz Fischer
9421aeda95SAlan Tullconfig FPGA_BRIDGE
9521aeda95SAlan Tull	tristate "FPGA Bridge Framework"
9621aeda95SAlan Tull	help
9721aeda95SAlan Tull	  Say Y here if you want to support bridges connected between host
9821aeda95SAlan Tull	  processors and FPGAs or between FPGAs.
9921aeda95SAlan Tull
100e5f8efa5SAlan Tullconfig SOCFPGA_FPGA_BRIDGE
101e5f8efa5SAlan Tull	tristate "Altera SoCFPGA FPGA Bridges"
1023a1fef70SKrzysztof Kozlowski	depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
103e5f8efa5SAlan Tull	help
104e5f8efa5SAlan Tull	  Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
105e5f8efa5SAlan Tull	  devices.
106e5f8efa5SAlan Tull
107ca24a648SAlan Tullconfig ALTERA_FREEZE_BRIDGE
108ca24a648SAlan Tull	tristate "Altera FPGA Freeze Bridge"
10938cd7ad5SAlan Tull	depends on FPGA_BRIDGE && HAS_IOMEM
110ca24a648SAlan Tull	help
111ca24a648SAlan Tull	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
112ca24a648SAlan Tull	  freeze bridge is a bridge that exists in the FPGA fabric to
113ca24a648SAlan Tull	  isolate one region of the FPGA from the busses while that
114ca24a648SAlan Tull	  region is being reprogrammed.
115ca24a648SAlan Tull
1167e961c12SMoritz Fischerconfig XILINX_PR_DECOUPLER
1177e961c12SMoritz Fischer	tristate "Xilinx LogiCORE PR Decoupler"
1187e961c12SMoritz Fischer	depends on FPGA_BRIDGE
1197e961c12SMoritz Fischer	depends on HAS_IOMEM
1207e961c12SMoritz Fischer	help
12130a2ac9aSNava kishore Manne	  Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
1225f1895e0SColin Ian King	  or Xilinx Dynamic Function eXchange AIX Shutdown Manager.
1237e961c12SMoritz Fischer	  The PR Decoupler exists in the FPGA fabric to isolate one
1247e961c12SMoritz Fischer	  region of the FPGA from the busses while that region is
1257e961c12SMoritz Fischer	  being reprogrammed during partial reconfig.
12630a2ac9aSNava kishore Manne	  The Dynamic Function eXchange AXI shutdown manager prevents
12730a2ac9aSNava kishore Manne	  AXI traffic from passing through the bridge. The controller
12830a2ac9aSNava kishore Manne	  safely handles AXI4MM and AXI4-Lite interfaces on a
12930a2ac9aSNava kishore Manne	  Reconfigurable Partition when it is undergoing dynamic
13030a2ac9aSNava kishore Manne	  reconfiguration, preventing the system deadlock that can
13130a2ac9aSNava kishore Manne	  occur if AXI transactions are interrupted by DFX.
1327e961c12SMoritz Fischer
13384e93f1dSAlan Tullconfig FPGA_REGION
13484e93f1dSAlan Tull	tristate "FPGA Region"
13584e93f1dSAlan Tull	depends on FPGA_BRIDGE
13684e93f1dSAlan Tull	help
137df82d2ecSTom Rix	  FPGA Region common code.  An FPGA Region controls an FPGA Manager
13884e93f1dSAlan Tull	  and the FPGA Bridges associated with either a reconfigurable
13984e93f1dSAlan Tull	  region of an FPGA or a whole FPGA.
14084e93f1dSAlan Tull
14184e93f1dSAlan Tullconfig OF_FPGA_REGION
14284e93f1dSAlan Tull	tristate "FPGA Region Device Tree Overlay Support"
14384e93f1dSAlan Tull	depends on OF && FPGA_REGION
14484e93f1dSAlan Tull	help
14584e93f1dSAlan Tull	  Support for loading FPGA images by applying a Device Tree
14684e93f1dSAlan Tull	  overlay.
14784e93f1dSAlan Tull
148543be3d8SWu Haoconfig FPGA_DFL
149543be3d8SWu Hao	tristate "FPGA Device Feature List (DFL) support"
150543be3d8SWu Hao	select FPGA_BRIDGE
151543be3d8SWu Hao	select FPGA_REGION
1521a16af33SDavid Gow	depends on HAS_IOMEM
153543be3d8SWu Hao	help
154543be3d8SWu Hao	  Device Feature List (DFL) defines a feature list structure that
155543be3d8SWu Hao	  creates a linked list of feature headers within the MMIO space
156543be3d8SWu Hao	  to provide an extensible way of adding features for FPGA.
157543be3d8SWu Hao	  Driver can walk through the feature headers to enumerate feature
158543be3d8SWu Hao	  devices (e.g. FPGA Management Engine, Port and Accelerator
159543be3d8SWu Hao	  Function Unit) and their private features for target FPGA devices.
160543be3d8SWu Hao
161543be3d8SWu Hao	  Select this option to enable common support for Field-Programmable
162543be3d8SWu Hao	  Gate Array (FPGA) solutions which implement Device Feature List.
163543be3d8SWu Hao	  It provides enumeration APIs and feature device infrastructure.
164543be3d8SWu Hao
165322ddebeSKang Luweiconfig FPGA_DFL_FME
166322ddebeSKang Luwei	tristate "FPGA DFL FME Driver"
167724142f8SWu Hao	depends on FPGA_DFL && HWMON && PERF_EVENTS
168322ddebeSKang Luwei	help
169322ddebeSKang Luwei	  The FPGA Management Engine (FME) is a feature device implemented
170322ddebeSKang Luwei	  under Device Feature List (DFL) framework. Select this option to
171322ddebeSKang Luwei	  enable the platform device driver for FME which implements all
172322ddebeSKang Luwei	  FPGA platform level management features. There shall be one FME
173322ddebeSKang Luwei	  per DFL based FPGA device.
174322ddebeSKang Luwei
175af275ec6SWu Haoconfig FPGA_DFL_FME_MGR
176af275ec6SWu Hao	tristate "FPGA DFL FME Manager Driver"
177af275ec6SWu Hao	depends on FPGA_DFL_FME && HAS_IOMEM
178af275ec6SWu Hao	help
179af275ec6SWu Hao	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
180af275ec6SWu Hao
181de892dffSWu Haoconfig FPGA_DFL_FME_BRIDGE
182de892dffSWu Hao	tristate "FPGA DFL FME Bridge Driver"
183de892dffSWu Hao	depends on FPGA_DFL_FME && HAS_IOMEM
184de892dffSWu Hao	help
185de892dffSWu Hao	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
186de892dffSWu Hao
187bb61b9beSWu Haoconfig FPGA_DFL_FME_REGION
188bb61b9beSWu Hao	tristate "FPGA DFL FME Region Driver"
189bb61b9beSWu Hao	depends on FPGA_DFL_FME && HAS_IOMEM
190bb61b9beSWu Hao	help
191bb61b9beSWu Hao	  Say Y to enable FPGA Region driver for FPGA Management Engine.
192bb61b9beSWu Hao
1931a1527cfSWu Haoconfig FPGA_DFL_AFU
1941a1527cfSWu Hao	tristate "FPGA DFL AFU Driver"
1951a1527cfSWu Hao	depends on FPGA_DFL
1961a1527cfSWu Hao	help
1971a1527cfSWu Hao	  This is the driver for FPGA Accelerated Function Unit (AFU) which
1981a1527cfSWu Hao	  implements AFU and Port management features. A User AFU connects
1991a1527cfSWu Hao	  to the FPGA infrastructure via a Port. There may be more than one
2001a1527cfSWu Hao	  Port/AFU per DFL based FPGA device.
2011a1527cfSWu Hao
20256172ab3SXu Yilunconfig FPGA_DFL_NIOS_INTEL_PAC_N3000
20356172ab3SXu Yilun	tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
20456172ab3SXu Yilun	depends on FPGA_DFL
20556172ab3SXu Yilun	select REGMAP
20656172ab3SXu Yilun	help
20756172ab3SXu Yilun	  This is the driver for the N3000 Nios private feature on Intel
20856172ab3SXu Yilun	  PAC (Programmable Acceleration Card) N3000. It communicates
20956172ab3SXu Yilun	  with the embedded Nios processor to configure the retimers on
21056172ab3SXu Yilun	  the card. It also instantiates the SPI master (spi-altera) for
21156172ab3SXu Yilun	  the card's BMC (Board Management Controller).
21256172ab3SXu Yilun
21372ddd9f3SZhang Yiconfig FPGA_DFL_PCI
21472ddd9f3SZhang Yi	tristate "FPGA DFL PCIe Device Driver"
21572ddd9f3SZhang Yi	depends on PCI && FPGA_DFL
21672ddd9f3SZhang Yi	help
21772ddd9f3SZhang Yi	  Select this option to enable PCIe driver for PCIe-based
21872ddd9f3SZhang Yi	  Field-Programmable Gate Array (FPGA) solutions which implement
21972ddd9f3SZhang Yi	  the Device Feature List (DFL). This driver provides interfaces
22072ddd9f3SZhang Yi	  for userspace applications to configure, enumerate, open and access
22172ddd9f3SZhang Yi	  FPGA accelerators on the FPGA DFL devices, enables system level
22272ddd9f3SZhang Yi	  management functions such as FPGA partial reconfiguration, power
22372ddd9f3SZhang Yi	  management and virtualization with DFL framework and DFL feature
22472ddd9f3SZhang Yi	  device drivers.
22572ddd9f3SZhang Yi
22672ddd9f3SZhang Yi	  To compile this as a module, choose M here.
22772ddd9f3SZhang Yi
228c09f7471SNava kishore Manneconfig FPGA_MGR_ZYNQMP_FPGA
229c09f7471SNava kishore Manne	tristate "Xilinx ZynqMP FPGA"
2306a47d6efSArnd Bergmann	depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
231c09f7471SNava kishore Manne	help
232c09f7471SNava kishore Manne	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
233c09f7471SNava kishore Manne	  This driver uses the processor configuration port(PCAP)
234c09f7471SNava kishore Manne	  to configure the programmable logic(PL) through PS
235c09f7471SNava kishore Manne	  on ZynqMP SoC.
236c09f7471SNava kishore Manne
23701c54e62SNava kishore Manneconfig FPGA_MGR_VERSAL_FPGA
23801c54e62SNava kishore Manne	tristate "Xilinx Versal FPGA"
23901c54e62SNava kishore Manne	depends on ARCH_ZYNQMP || COMPILE_TEST
24001c54e62SNava kishore Manne	help
24101c54e62SNava kishore Manne	  Select this option to enable FPGA manager driver support for
24201c54e62SNava kishore Manne	  Xilinx Versal SoC. This driver uses the firmware interface to
24301c54e62SNava kishore Manne	  configure the programmable logic(PL).
24401c54e62SNava kishore Manne
24501c54e62SNava kishore Manne	  To compile this as a module, choose M here.
246bdf86d0eSRuss Weight
247bdf86d0eSRuss Weightconfig FPGA_M10_BMC_SEC_UPDATE
248bdf86d0eSRuss Weight	tristate "Intel MAX10 BMC Secure Update driver"
249603aed8fSIlpo Järvinen	depends on MFD_INTEL_M10_BMC_CORE
250dfd10332SRuss Weight	select FW_LOADER
251dfd10332SRuss Weight	select FW_UPLOAD
252bdf86d0eSRuss Weight	help
253bdf86d0eSRuss Weight	  Secure update support for the Intel MAX10 board management
254bdf86d0eSRuss Weight	  controller.
255bdf86d0eSRuss Weight
256bdf86d0eSRuss Weight	  This is a subdriver of the Intel MAX10 board management controller
257bdf86d0eSRuss Weight	  (BMC) and provides support for secure updates for the BMC image,
258bdf86d0eSRuss Weight	  the FPGA image, the Root Entry Hashes, etc.
259bdf86d0eSRuss Weight
2605f8d4a90SIvan Bornyakovconfig FPGA_MGR_MICROCHIP_SPI
2615f8d4a90SIvan Bornyakov	tristate "Microchip Polarfire SPI FPGA manager"
2625f8d4a90SIvan Bornyakov	depends on SPI
2635f8d4a90SIvan Bornyakov	help
2645f8d4a90SIvan Bornyakov	  FPGA manager driver support for Microchip Polarfire FPGAs
2655f8d4a90SIvan Bornyakov	  programming over slave SPI interface with .dat formatted
2665f8d4a90SIvan Bornyakov	  bitstream image.
2675f8d4a90SIvan Bornyakov
268463dd43bSIvan Bornyakovconfig FPGA_MGR_LATTICE_SYSCONFIG
269463dd43bSIvan Bornyakov	tristate
270463dd43bSIvan Bornyakov
271463dd43bSIvan Bornyakovconfig FPGA_MGR_LATTICE_SYSCONFIG_SPI
272463dd43bSIvan Bornyakov	tristate "Lattice sysCONFIG SPI FPGA manager"
273463dd43bSIvan Bornyakov	depends on SPI
274463dd43bSIvan Bornyakov	select FPGA_MGR_LATTICE_SYSCONFIG
275463dd43bSIvan Bornyakov	help
276463dd43bSIvan Bornyakov	  FPGA manager driver support for Lattice FPGAs programming over slave
277463dd43bSIvan Bornyakov	  SPI sysCONFIG interface.
278463dd43bSIvan Bornyakov
279*3969f645SMarco Paganisource "drivers/fpga/tests/Kconfig"
280*3969f645SMarco Pagani
281fab6266eSAlan Tullendif # FPGA
282