1d524dac9SGrant Likely d) Xilinx IP cores 2d524dac9SGrant Likely 3d524dac9SGrant Likely The Xilinx EDK toolchain ships with a set of IP cores (devices) for use 4d524dac9SGrant Likely in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range 5d524dac9SGrant Likely of standard device types (network, serial, etc.) and miscellaneous 6d524dac9SGrant Likely devices (gpio, LCD, spi, etc). Also, since these devices are 7d524dac9SGrant Likely implemented within the fpga fabric every instance of the device can be 8d524dac9SGrant Likely synthesised with different options that change the behaviour. 9d524dac9SGrant Likely 10d524dac9SGrant Likely Each IP-core has a set of parameters which the FPGA designer can use to 11d524dac9SGrant Likely control how the core is synthesized. Historically, the EDK tool would 12d524dac9SGrant Likely extract the device parameters relevant to device drivers and copy them 13d524dac9SGrant Likely into an 'xparameters.h' in the form of #define symbols. This tells the 14d524dac9SGrant Likely device drivers how the IP cores are configured, but it requires the kernel 15d524dac9SGrant Likely to be recompiled every time the FPGA bitstream is resynthesized. 16d524dac9SGrant Likely 17d524dac9SGrant Likely The new approach is to export the parameters into the device tree and 18d524dac9SGrant Likely generate a new device tree each time the FPGA bitstream changes. The 19d524dac9SGrant Likely parameters which used to be exported as #defines will now become 20d524dac9SGrant Likely properties of the device node. In general, device nodes for IP-cores 21d524dac9SGrant Likely will take the following form: 22d524dac9SGrant Likely 23d524dac9SGrant Likely (name): (generic-name)@(base-address) { 24d524dac9SGrant Likely compatible = "xlnx,(ip-core-name)-(HW_VER)" 25d524dac9SGrant Likely [, (list of compatible devices), ...]; 26d524dac9SGrant Likely reg = <(baseaddr) (size)>; 27d524dac9SGrant Likely interrupt-parent = <&interrupt-controller-phandle>; 28d524dac9SGrant Likely interrupts = < ... >; 29d524dac9SGrant Likely xlnx,(parameter1) = "(string-value)"; 30d524dac9SGrant Likely xlnx,(parameter2) = <(int-value)>; 31d524dac9SGrant Likely }; 32d524dac9SGrant Likely 33d524dac9SGrant Likely (generic-name): an open firmware-style name that describes the 34d524dac9SGrant Likely generic class of device. Preferably, this is one word, such 35d524dac9SGrant Likely as 'serial' or 'ethernet'. 36d524dac9SGrant Likely (ip-core-name): the name of the ip block (given after the BEGIN 37d524dac9SGrant Likely directive in system.mhs). Should be in lowercase 38d524dac9SGrant Likely and all underscores '_' converted to dashes '-'. 39d524dac9SGrant Likely (name): is derived from the "PARAMETER INSTANCE" value. 40d524dac9SGrant Likely (parameter#): C_* parameters from system.mhs. The C_ prefix is 41d524dac9SGrant Likely dropped from the parameter name, the name is converted 42d524dac9SGrant Likely to lowercase and all underscore '_' characters are 43d524dac9SGrant Likely converted to dashes '-'. 44d524dac9SGrant Likely (baseaddr): the baseaddr parameter value (often named C_BASEADDR). 45d524dac9SGrant Likely (HW_VER): from the HW_VER parameter. 46d524dac9SGrant Likely (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). 47d524dac9SGrant Likely 48d524dac9SGrant Likely Typically, the compatible list will include the exact IP core version 49d524dac9SGrant Likely followed by an older IP core version which implements the same 50d524dac9SGrant Likely interface or any other device with the same interface. 51d524dac9SGrant Likely 52791d3ef2SRob Herring 'reg' and 'interrupts' are all optional properties. 53d524dac9SGrant Likely 54d524dac9SGrant Likely For example, the following block from system.mhs: 55d524dac9SGrant Likely 56d524dac9SGrant Likely BEGIN opb_uartlite 57d524dac9SGrant Likely PARAMETER INSTANCE = opb_uartlite_0 58d524dac9SGrant Likely PARAMETER HW_VER = 1.00.b 59d524dac9SGrant Likely PARAMETER C_BAUDRATE = 115200 60d524dac9SGrant Likely PARAMETER C_DATA_BITS = 8 61d524dac9SGrant Likely PARAMETER C_ODD_PARITY = 0 62d524dac9SGrant Likely PARAMETER C_USE_PARITY = 0 63d524dac9SGrant Likely PARAMETER C_CLK_FREQ = 50000000 64d524dac9SGrant Likely PARAMETER C_BASEADDR = 0xEC100000 65d524dac9SGrant Likely PARAMETER C_HIGHADDR = 0xEC10FFFF 66d524dac9SGrant Likely BUS_INTERFACE SOPB = opb_7 67d524dac9SGrant Likely PORT OPB_Clk = CLK_50MHz 68d524dac9SGrant Likely PORT Interrupt = opb_uartlite_0_Interrupt 69d524dac9SGrant Likely PORT RX = opb_uartlite_0_RX 70d524dac9SGrant Likely PORT TX = opb_uartlite_0_TX 71d524dac9SGrant Likely PORT OPB_Rst = sys_bus_reset_0 72d524dac9SGrant Likely END 73d524dac9SGrant Likely 74d524dac9SGrant Likely becomes the following device tree node: 75d524dac9SGrant Likely 76d524dac9SGrant Likely opb_uartlite_0: serial@ec100000 { 77d524dac9SGrant Likely device_type = "serial"; 78d524dac9SGrant Likely compatible = "xlnx,opb-uartlite-1.00.b"; 79d524dac9SGrant Likely reg = <ec100000 10000>; 80d524dac9SGrant Likely interrupt-parent = <&opb_intc_0>; 81d524dac9SGrant Likely interrupts = <1 0>; // got this from the opb_intc parameters 82d524dac9SGrant Likely current-speed = <d#115200>; // standard serial device prop 83d524dac9SGrant Likely clock-frequency = <d#50000000>; // standard serial device prop 84d524dac9SGrant Likely xlnx,data-bits = <8>; 85d524dac9SGrant Likely xlnx,odd-parity = <0>; 86d524dac9SGrant Likely xlnx,use-parity = <0>; 87d524dac9SGrant Likely }; 88d524dac9SGrant Likely 89d524dac9SGrant Likely That covers the general approach to binding xilinx IP cores into the 90d524dac9SGrant Likely device tree. The following are bindings for specific devices: 91d524dac9SGrant Likely 92d524dac9SGrant Likely i) Xilinx ML300 Framebuffer 93d524dac9SGrant Likely 94d524dac9SGrant Likely Simple framebuffer device from the ML300 reference design (also on the 95d524dac9SGrant Likely ML403 reference design as well as others). 96d524dac9SGrant Likely 97d524dac9SGrant Likely Optional properties: 98d524dac9SGrant Likely - resolution = <xres yres> : pixel resolution of framebuffer. Some 99d524dac9SGrant Likely implementations use a different resolution. 100d524dac9SGrant Likely Default is <d#640 d#480> 101d524dac9SGrant Likely - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. 102d524dac9SGrant Likely Default is <d#1024 d#480>. 103d524dac9SGrant Likely - rotate-display (empty) : rotate display 180 degrees. 104d524dac9SGrant Likely 105d524dac9SGrant Likely ii) Xilinx SystemACE 106d524dac9SGrant Likely 107d524dac9SGrant Likely The Xilinx SystemACE device is used to program FPGAs from an FPGA 108d524dac9SGrant Likely bitstream stored on a CF card. It can also be used as a generic CF 109d524dac9SGrant Likely interface device. 110d524dac9SGrant Likely 111d524dac9SGrant Likely Optional properties: 112d524dac9SGrant Likely - 8-bit (empty) : Set this property for SystemACE in 8 bit mode 113d524dac9SGrant Likely 114d524dac9SGrant Likely iii) Xilinx EMAC and Xilinx TEMAC 115d524dac9SGrant Likely 116d524dac9SGrant Likely Xilinx Ethernet devices. In addition to general xilinx properties 117d524dac9SGrant Likely listed above, nodes for these devices should include a phy-handle 118d524dac9SGrant Likely property, and may include other common network device properties 119d524dac9SGrant Likely like local-mac-address. 120d524dac9SGrant Likely 121d524dac9SGrant Likely iv) Xilinx Uartlite 122d524dac9SGrant Likely 123d524dac9SGrant Likely Xilinx uartlite devices are simple fixed speed serial ports. 124d524dac9SGrant Likely 125d524dac9SGrant Likely Required properties: 126d524dac9SGrant Likely - current-speed : Baud rate of uartlite 127d524dac9SGrant Likely 128d524dac9SGrant Likely v) Xilinx hwicap 129d524dac9SGrant Likely 130d524dac9SGrant Likely Xilinx hwicap devices provide access to the configuration logic 131d524dac9SGrant Likely of the FPGA through the Internal Configuration Access Port 132d524dac9SGrant Likely (ICAP). The ICAP enables partial reconfiguration of the FPGA, 133d524dac9SGrant Likely readback of the configuration information, and some control over 134d524dac9SGrant Likely 'warm boots' of the FPGA fabric. 135d524dac9SGrant Likely 136d524dac9SGrant Likely Required properties: 137d524dac9SGrant Likely - xlnx,family : The family of the FPGA, necessary since the 138d524dac9SGrant Likely capabilities of the underlying ICAP hardware 139d524dac9SGrant Likely differ between different families. May be 140d524dac9SGrant Likely 'virtex2p', 'virtex4', or 'virtex5'. 1415cb95faeSNava kishore Manne - compatible : should contain "xlnx,xps-hwicap-1.00.a" or 1425cb95faeSNava kishore Manne "xlnx,opb-hwicap-1.00.b". 143d524dac9SGrant Likely 144d524dac9SGrant Likely vi) Xilinx Uart 16550 145d524dac9SGrant Likely 146d524dac9SGrant Likely Xilinx UART 16550 devices are very similar to the NS16550 but with 147d524dac9SGrant Likely different register spacing and an offset from the base address. 148d524dac9SGrant Likely 149d524dac9SGrant Likely Required properties: 150d524dac9SGrant Likely - clock-frequency : Frequency of the clock input 151d524dac9SGrant Likely - reg-offset : A value of 3 is required 152d524dac9SGrant Likely - reg-shift : A value of 2 is required 153d524dac9SGrant Likely 154d524dac9SGrant Likely vii) Xilinx USB Host controller 155d524dac9SGrant Likely 156d524dac9SGrant Likely The Xilinx USB host controller is EHCI compatible but with a different 157d524dac9SGrant Likely base address for the EHCI registers, and it is always a big-endian 158d524dac9SGrant Likely USB Host controller. The hardware can be configured as high speed only, 159d524dac9SGrant Likely or high speed/full speed hybrid. 160d524dac9SGrant Likely 161d524dac9SGrant Likely Required properties: 162d524dac9SGrant Likely - xlnx,support-usb-fs: A value 0 means the core is built as high speed 163d524dac9SGrant Likely only. A value 1 means the core also supports 164d524dac9SGrant Likely full speed devices. 165d524dac9SGrant Likely 166