1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22678059eSSiva Durga Prasad Paladugu /* 32678059eSSiva Durga Prasad Paladugu * Configuration for Xilinx ZynqMP eMMC Flash utility 42678059eSSiva Durga Prasad Paladugu * 52678059eSSiva Durga Prasad Paladugu * (C) Copyright 2018 Xilinx, Inc. 62678059eSSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 72678059eSSiva Durga Prasad Paladugu * Siva Durga Prasad Paladugu <sivadur@xilinx.com> 82678059eSSiva Durga Prasad Paladugu */ 92678059eSSiva Durga Prasad Paladugu 102678059eSSiva Durga Prasad Paladugu #ifndef __CONFIG_ZYNQMP_MINI_EMMC_H 112678059eSSiva Durga Prasad Paladugu #define __CONFIG_ZYNQMP_MINI_EMMC_H 122678059eSSiva Durga Prasad Paladugu 132678059eSSiva Durga Prasad Paladugu #include <configs/xilinx_zynqmp_mini.h> 142678059eSSiva Durga Prasad Paladugu 152678059eSSiva Durga Prasad Paladugu #define CONFIG_SYS_ICACHE_OFF 162678059eSSiva Durga Prasad Paladugu #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 172678059eSSiva Durga Prasad Paladugu #define CONFIG_SYS_MALLOC_LEN 0x800000 182678059eSSiva Durga Prasad Paladugu 192678059eSSiva Durga Prasad Paladugu #endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ 20