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/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/gpio/phosphor-gpio-monitor/
H A Ddeassert-uart-switch-button11 uart_sel=$((uart_msb+(uart_lsb<<1)))
21 set_postcode_leds "$uart_sel"
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2712.c656 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15),
901 GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20),
902 GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21),
903 GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22),
904 GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23),
918 GATE_PERI1(CLK_PERI_UART4, "per_uart4", "uart_sel", 9),
919 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", "uart_sel", 11),
920 GATE_PERI1(CLK_PERI_GMAC, "per_gmac", "uart_sel", 12),
921 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", "uart_sel", 14),
922 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", "uart_sel", 15),
[all …]
H A Dclk-mt6797.c338 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
467 GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
468 GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
469 GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
470 GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
H A Dclk-mt8365.c429 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
690 GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22),
691 GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23),
692 GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24),
693 GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26),
H A Dclk-mt8183.c491 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
719 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
720 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
721 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
722 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
H A Dclk-mt8192.c598 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
806 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
807 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
808 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
809 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
H A Dclk-mt6779.c684 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
924 "uart_sel", 22),
926 "uart_sel", 23),
928 "uart_sel", 24),
930 "uart_sel", 25),
H A Dclk-mt8173-pericfg.c38 "uart_sel",
H A Dclk-mt7981-topckgen.c70 FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
301 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
H A Dclk-mt6795-pericfg.c29 "uart_sel",
H A Dclk-mt8135.c375 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
496 "uart_sel",
H A Dclk-mt7986-infracfg.c25 "uart_sel" };
H A Dclk-mt7981-infracfg.c27 "uart_sel" };
H A Dclk-mt7986-topckgen.c184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
H A Dclk-mt6765.c141 FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
402 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx35.c65 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, enumerator
138 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); in _mx35_clocks_init()
139 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); in _mx35_clocks_init()
H A Dclk-imx6sll.c209 …hws[IMX6SLL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE… in imx6sll_clocks_init()
229 hws[IMX6SLL_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); in imx6sll_clocks_init()
H A Dclk-imx6sl.c322 …hws[IMX6SL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sel… in imx6sl_clocks_init()
361 …hws[IMX6SL_CLK_UART_ROOT] = imx_clk_hw_divider("uart_root", "uart_sel", b… in imx6sl_clocks_init()
/openbmc/u-boot/board/freescale/ls1046ardb/
H A Dcpld.c104 printf("uart_sel = %x\n", CPLD_READ(uart_sel)); in cpld_dump_regs()
H A Dcpld.h23 u8 uart_sel; /* 0x9 - UART1 Connection Control Register */ member
/openbmc/u-boot/board/freescale/ls1043ardb/
H A Dcpld.c111 printf("uart_sel = %x\n", CPLD_READ(uart_sel)); in cpld_dump_regs()
H A Dcpld.h22 u8 uart_sel; /* 0x9 - */ member
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx35-clock.yaml32 uart_sel 13
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S406 /* UART_SEL GPK0[5] at S5PC100 */
428 /* UART_SEL MP0_5[7] at S5PC110 */
/openbmc/u-boot/board/samsung/trats/
H A Dtrats.c386 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ in exynos_uart_init()
387 gpio_request(EXYNOS4_GPIO_Y47, "uart_sel"); in exynos_uart_init()

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