1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2f3a8e2b7SMingkai Hu /*
3f3a8e2b7SMingkai Hu * Copyright 2015 Freescale Semiconductor
4f3a8e2b7SMingkai Hu *
5f3a8e2b7SMingkai Hu * Freescale LS1043ARDB board-specific CPLD controlling supports.
6f3a8e2b7SMingkai Hu */
7f3a8e2b7SMingkai Hu
8f3a8e2b7SMingkai Hu #include <common.h>
9f3a8e2b7SMingkai Hu #include <command.h>
10f3a8e2b7SMingkai Hu #include <asm/io.h>
11f3a8e2b7SMingkai Hu #include "cpld.h"
12f3a8e2b7SMingkai Hu
cpld_read(unsigned int reg)13f3a8e2b7SMingkai Hu u8 cpld_read(unsigned int reg)
14f3a8e2b7SMingkai Hu {
15f3a8e2b7SMingkai Hu void *p = (void *)CONFIG_SYS_CPLD_BASE;
16f3a8e2b7SMingkai Hu
17f3a8e2b7SMingkai Hu return in_8(p + reg);
18f3a8e2b7SMingkai Hu }
19f3a8e2b7SMingkai Hu
cpld_write(unsigned int reg,u8 value)20f3a8e2b7SMingkai Hu void cpld_write(unsigned int reg, u8 value)
21f3a8e2b7SMingkai Hu {
22f3a8e2b7SMingkai Hu void *p = (void *)CONFIG_SYS_CPLD_BASE;
23f3a8e2b7SMingkai Hu
24f3a8e2b7SMingkai Hu out_8(p + reg, value);
25f3a8e2b7SMingkai Hu }
26f3a8e2b7SMingkai Hu
27f3a8e2b7SMingkai Hu /* Set the boot bank to the alternate bank */
cpld_set_altbank(void)28f3a8e2b7SMingkai Hu void cpld_set_altbank(void)
29f3a8e2b7SMingkai Hu {
30869bf868SQianyu Gong u16 reg = CPLD_CFG_RCW_SRC_NOR;
31f3a8e2b7SMingkai Hu u8 reg4 = CPLD_READ(soft_mux_on);
32869bf868SQianyu Gong u8 reg5 = (u8)(reg >> 1);
33869bf868SQianyu Gong u8 reg6 = (u8)(reg & 1);
34f3a8e2b7SMingkai Hu u8 reg7 = CPLD_READ(vbank);
35f3a8e2b7SMingkai Hu
36869bf868SQianyu Gong cpld_rev_bit(®5);
37869bf868SQianyu Gong
38869bf868SQianyu Gong CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
39869bf868SQianyu Gong
40869bf868SQianyu Gong CPLD_WRITE(cfg_rcw_src1, reg5);
41869bf868SQianyu Gong CPLD_WRITE(cfg_rcw_src2, reg6);
42f3a8e2b7SMingkai Hu
43f3a8e2b7SMingkai Hu reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
44f3a8e2b7SMingkai Hu CPLD_WRITE(vbank, reg7);
45f3a8e2b7SMingkai Hu
46f3a8e2b7SMingkai Hu CPLD_WRITE(system_rst, 1);
47f3a8e2b7SMingkai Hu }
48f3a8e2b7SMingkai Hu
49f3a8e2b7SMingkai Hu /* Set the boot bank to the default bank */
cpld_set_defbank(void)50f3a8e2b7SMingkai Hu void cpld_set_defbank(void)
51f3a8e2b7SMingkai Hu {
52869bf868SQianyu Gong u16 reg = CPLD_CFG_RCW_SRC_NOR;
53869bf868SQianyu Gong u8 reg4 = CPLD_READ(soft_mux_on);
54869bf868SQianyu Gong u8 reg5 = (u8)(reg >> 1);
55869bf868SQianyu Gong u8 reg6 = (u8)(reg & 1);
56869bf868SQianyu Gong
57869bf868SQianyu Gong cpld_rev_bit(®5);
58869bf868SQianyu Gong
59869bf868SQianyu Gong CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
60869bf868SQianyu Gong
61869bf868SQianyu Gong CPLD_WRITE(cfg_rcw_src1, reg5);
62869bf868SQianyu Gong CPLD_WRITE(cfg_rcw_src2, reg6);
63869bf868SQianyu Gong
64869bf868SQianyu Gong CPLD_WRITE(vbank, 0);
65869bf868SQianyu Gong
66869bf868SQianyu Gong CPLD_WRITE(system_rst, 1);
67f3a8e2b7SMingkai Hu }
68f3a8e2b7SMingkai Hu
cpld_set_nand(void)693ad44729SGong Qianyu void cpld_set_nand(void)
703ad44729SGong Qianyu {
713ad44729SGong Qianyu u16 reg = CPLD_CFG_RCW_SRC_NAND;
723ad44729SGong Qianyu u8 reg5 = (u8)(reg >> 1);
733ad44729SGong Qianyu u8 reg6 = (u8)(reg & 1);
743ad44729SGong Qianyu
753ad44729SGong Qianyu cpld_rev_bit(®5);
763ad44729SGong Qianyu
773ad44729SGong Qianyu CPLD_WRITE(soft_mux_on, 1);
783ad44729SGong Qianyu
793ad44729SGong Qianyu CPLD_WRITE(cfg_rcw_src1, reg5);
803ad44729SGong Qianyu CPLD_WRITE(cfg_rcw_src2, reg6);
813ad44729SGong Qianyu
823ad44729SGong Qianyu CPLD_WRITE(system_rst, 1);
833ad44729SGong Qianyu }
843ad44729SGong Qianyu
cpld_set_sd(void)85c7ca8b07SGong Qianyu void cpld_set_sd(void)
86c7ca8b07SGong Qianyu {
87c7ca8b07SGong Qianyu u16 reg = CPLD_CFG_RCW_SRC_SD;
88c7ca8b07SGong Qianyu u8 reg5 = (u8)(reg >> 1);
89c7ca8b07SGong Qianyu u8 reg6 = (u8)(reg & 1);
90c7ca8b07SGong Qianyu
91c7ca8b07SGong Qianyu cpld_rev_bit(®5);
92c7ca8b07SGong Qianyu
93c7ca8b07SGong Qianyu CPLD_WRITE(soft_mux_on, 1);
94c7ca8b07SGong Qianyu
95c7ca8b07SGong Qianyu CPLD_WRITE(cfg_rcw_src1, reg5);
96c7ca8b07SGong Qianyu CPLD_WRITE(cfg_rcw_src2, reg6);
97c7ca8b07SGong Qianyu
98c7ca8b07SGong Qianyu CPLD_WRITE(system_rst, 1);
99c7ca8b07SGong Qianyu }
100f3a8e2b7SMingkai Hu #ifdef DEBUG
cpld_dump_regs(void)101f3a8e2b7SMingkai Hu static void cpld_dump_regs(void)
102f3a8e2b7SMingkai Hu {
103f3a8e2b7SMingkai Hu printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
104f3a8e2b7SMingkai Hu printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
105f3a8e2b7SMingkai Hu printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
106f3a8e2b7SMingkai Hu printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
107f3a8e2b7SMingkai Hu printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
108f3a8e2b7SMingkai Hu printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
109f3a8e2b7SMingkai Hu printf("vbank = %x\n", CPLD_READ(vbank));
110f3a8e2b7SMingkai Hu printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
111f3a8e2b7SMingkai Hu printf("uart_sel = %x\n", CPLD_READ(uart_sel));
112f3a8e2b7SMingkai Hu printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
113f3a8e2b7SMingkai Hu printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel));
114f3a8e2b7SMingkai Hu printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel));
115f3a8e2b7SMingkai Hu printf("status_led = %x\n", CPLD_READ(status_led));
116f3a8e2b7SMingkai Hu putc('\n');
117f3a8e2b7SMingkai Hu }
118f3a8e2b7SMingkai Hu #endif
119f3a8e2b7SMingkai Hu
cpld_rev_bit(unsigned char * value)120f3a8e2b7SMingkai Hu void cpld_rev_bit(unsigned char *value)
121f3a8e2b7SMingkai Hu {
122f3a8e2b7SMingkai Hu u8 rev_val, val;
123f3a8e2b7SMingkai Hu int i;
124f3a8e2b7SMingkai Hu
125f3a8e2b7SMingkai Hu val = *value;
126f3a8e2b7SMingkai Hu rev_val = val & 1;
127f3a8e2b7SMingkai Hu for (i = 1; i <= 7; i++) {
128f3a8e2b7SMingkai Hu val >>= 1;
129f3a8e2b7SMingkai Hu rev_val <<= 1;
130f3a8e2b7SMingkai Hu rev_val |= val & 1;
131f3a8e2b7SMingkai Hu }
132f3a8e2b7SMingkai Hu
133f3a8e2b7SMingkai Hu *value = rev_val;
134f3a8e2b7SMingkai Hu }
135f3a8e2b7SMingkai Hu
do_cpld(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])136f3a8e2b7SMingkai Hu int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
137f3a8e2b7SMingkai Hu {
138f3a8e2b7SMingkai Hu int rc = 0;
139f3a8e2b7SMingkai Hu
140f3a8e2b7SMingkai Hu if (argc <= 1)
141f3a8e2b7SMingkai Hu return cmd_usage(cmdtp);
142f3a8e2b7SMingkai Hu
143f3a8e2b7SMingkai Hu if (strcmp(argv[1], "reset") == 0) {
144f3a8e2b7SMingkai Hu if (strcmp(argv[2], "altbank") == 0)
145f3a8e2b7SMingkai Hu cpld_set_altbank();
1463ad44729SGong Qianyu else if (strcmp(argv[2], "nand") == 0)
1473ad44729SGong Qianyu cpld_set_nand();
148c7ca8b07SGong Qianyu else if (strcmp(argv[2], "sd") == 0)
149c7ca8b07SGong Qianyu cpld_set_sd();
150f3a8e2b7SMingkai Hu else
151f3a8e2b7SMingkai Hu cpld_set_defbank();
152f3a8e2b7SMingkai Hu #ifdef DEBUG
153f3a8e2b7SMingkai Hu } else if (strcmp(argv[1], "dump") == 0) {
154f3a8e2b7SMingkai Hu cpld_dump_regs();
155f3a8e2b7SMingkai Hu #endif
156f3a8e2b7SMingkai Hu } else {
157f3a8e2b7SMingkai Hu rc = cmd_usage(cmdtp);
158f3a8e2b7SMingkai Hu }
159f3a8e2b7SMingkai Hu
160f3a8e2b7SMingkai Hu return rc;
161f3a8e2b7SMingkai Hu }
162f3a8e2b7SMingkai Hu
163f3a8e2b7SMingkai Hu U_BOOT_CMD(
164f3a8e2b7SMingkai Hu cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
165f3a8e2b7SMingkai Hu "Reset the board or alternate bank",
166f3a8e2b7SMingkai Hu "reset: reset to default bank\n"
167f3a8e2b7SMingkai Hu "cpld reset altbank: reset to alternate bank\n"
1683ad44729SGong Qianyu "cpld reset nand: reset to boot from NAND flash\n"
169c7ca8b07SGong Qianyu "cpld reset sd: reset to boot from SD card\n"
170f3a8e2b7SMingkai Hu #ifdef DEBUG
171f3a8e2b7SMingkai Hu "cpld dump - display the CPLD registers\n"
172f3a8e2b7SMingkai Hu #endif
173f3a8e2b7SMingkai Hu );
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