Lines Matching full:uart_sel
656 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15),
901 GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20),
902 GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21),
903 GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22),
904 GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23),
918 GATE_PERI1(CLK_PERI_UART4, "per_uart4", "uart_sel", 9),
919 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", "uart_sel", 11),
920 GATE_PERI1(CLK_PERI_GMAC, "per_gmac", "uart_sel", 12),
921 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", "uart_sel", 14),
922 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", "uart_sel", 15),
923 GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", "uart_sel", 16),