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/openbmc/qemu/hw/ssi/
H A Dxilinx_spips.c29 #include "hw/qdev-properties.h"
89 #define IXR_ALL ((1 << 13) - 1)
181 * or most recently executed command. So the generic fifo format is defined
218 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && in num_effective_busses()
219 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; in num_effective_busses()
226 for (i = 0; i < s->num_cs * s->num_busses; i++) { in xilinx_spips_update_cs()
227 bool old_state = s->cs_lines_state[i]; in xilinx_spips_update_cs()
231 s->cs_lines_state[i] = new_state; in xilinx_spips_update_cs()
232 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); in xilinx_spips_update_cs()
236 qemu_set_irq(s->cs_lines[i], !new_state); in xilinx_spips_update_cs()
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H A Dibex_spi_host.c32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
112 uint32_t data = s->regs[IBEX_SPI_HOST_STATUS]; in ibex_spi_rxfifo_reset()
113 /* Empty the RX FIFO and assert RXEMPTY */ in ibex_spi_rxfifo_reset()
114 fifo8_reset(&s->rx_fifo); in ibex_spi_rxfifo_reset()
117 s->regs[IBEX_SPI_HOST_STATUS] = data; in ibex_spi_rxfifo_reset()
122 uint32_t data = s->regs[IBEX_SPI_HOST_STATUS]; in ibex_spi_txfifo_reset()
123 /* Empty the TX FIFO and assert TXEMPTY */ in ibex_spi_txfifo_reset()
124 fifo8_reset(&s->tx_fifo); in ibex_spi_txfifo_reset()
127 s->regs[IBEX_SPI_HOST_STATUS] = data; in ibex_spi_txfifo_reset()
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/openbmc/u-boot/drivers/net/fm/
H A Dfm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
38 align_mask = align - 1; in fm_muram_alloc()
43 muram[fm_idx].alloc += (align - off); in fm_muram_alloc()
46 size += (align - off); in fm_muram_alloc()
71 * fm_upload_ucode - Fman microcode upload worker function
83 out_be32(&imem->iadd, IRAM_IADD_AIE); in fm_upload_ucode()
86 out_be32(&imem->idata, (be32_to_cpu(ucode[i]))); in fm_upload_ucode()
89 out_be32(&imem->iadd, 0); in fm_upload_ucode()
90 while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout) in fm_upload_ucode()
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/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm016-dc2 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
35 stdout-path = "serial0:115200n8";
86 phy-handle = <&phy0>;
87 phy-mode = "rgmii-id";
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H A Drk3036.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
13 interrupt-parent = <&gic>;
32 arm-pmu {
33 compatible = "arm,cortex-a7-pmu";
36 interrupt-affinity = <&cpu0>, <&cpu1>;
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H A Dda850-evm.dts4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
15 compatible = "ti,da850-evm", "ti,da850";
16 model = "DA850/AM1808/OMAP-L138 EVM";
19 stdout-path = &serial2;
30 backlight: backlight-pwm {
31 pinctrl-names = "default";
32 pinctrl-0 = <&ecap2_pins>;
33 power-supply = <&backlight_lcd>;
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H A Dimx6sx.dtsi9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6sx-pinfunc.h"
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
63 operating-points = <
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H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
16 * Also for U-Boot there must be a pre-existing /memory node.
55 compatible = "fsl,imx-ckil", "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <32768>;
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H A Dam335x-evm.dts2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
15 compatible = "ti,am335x-evm", "ti,am33xx";
18 stdout-path = &uart0;
19 tick-timer = &timer2;
24 cpu0-supply = <&vdd1_reg>;
34 compatible = "regulator-fixed";
35 regulator-name = "vbat";
36 regulator-min-microvolt = <5000000>;
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H A Drk3288-phycore-som.dtsi2 * Device tree file for Phytec phyCORE-RK3288 SoM
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/net/ti-dp83867.h>
50 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
67 ext_gmac: external-gmac-clock {
68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <125000000>;
71 clock-output-names = "ext_gmac";
75 compatible = "rockchip,rk3288-io-voltage-domain";
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H A Drk322x.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3228-cru.h>
11 #include <dt-bindings/thermal/thermal.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
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H A Dam335x-evmsk.dts2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
14 /dts-v1/;
17 #include <dt-bindings/pwm/pwm.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
21 model = "TI AM335x EVM-SK";
22 compatible = "ti,am335x-evmsk", "ti,am33xx";
25 stdout-path = &uart0;
26 tick-timer = &timer2;
31 cpu0-supply = <&vdd1_reg>;
41 compatible = "regulator-fixed";
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H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
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/openbmc/u-boot/arch/nios2/dts/
H A D3c120_devboard.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
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H A D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
12 compatible = "altr,niosii-max10";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 u-boot,dm-pre-reloc;
23 compatible = "altr,nios2-1.1";
25 interrupt-controller;
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/openbmc/qemu/pc-bios/dtb/
H A Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
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/openbmc/u-boot/drivers/usb/host/
H A Ddwc2.c1 // SPDX-License-Identifier: GPL-2.0+
58 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
87 uint32_t hwcfg2 = readl(&regs->ghwcfg2); in init_fslspclksel()
97 clrsetbits_le32(&regs->host_regs.hcfg, in init_fslspclksel()
103 * Flush a Tx FIFO.
106 * @param num Tx FIFO to flush.
108 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) in dwc_otg_flush_tx_fifo() argument
112 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), in dwc_otg_flush_tx_fifo()
113 &regs->grstctl); in dwc_otg_flush_tx_fifo()
114 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, in dwc_otg_flush_tx_fifo()
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/openbmc/u-boot/drivers/spi/
H A Dfsl_dspi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
6 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
33 /* max chipselect signals number */
39 /* tx/rx data wait timeout value, unit: us */
42 /* CTAR register pre-configure value */
51 /* CTAR register pre-configure mask */
61 * struct fsl_dspi_platdata - platform data for Freescale DSPI
76 * struct fsl_dspi_priv - private data for Freescale DSPI
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c1 // SPDX-License-Identifier: GPL-2.0
64 puts("DDR3 Training Sequence - Ver 5.7."); in ddr3_print_version()
90 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 1\n"); in ddr3_hw_training()
104 /* Ignore ECC errors - if ECC is enabled */ in ddr3_hw_training()
174 * Xor Bypass - ECC support in AXP is currently available for 1:1 in ddr3_hw_training()
184 DEBUG_MAIN_S("DDR3 Training Sequence - Run with PBS.\n"); in ddr3_hw_training()
186 DEBUG_MAIN_S("DDR3 Training Sequence - Run without PBS.\n"); in ddr3_hw_training()
197 /* Set low - 100Mhz DDR Frequency by HW */ in ddr3_hw_training()
198 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs High2Low)\n"); in ddr3_hw_training()
207 DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM Low WL - SKIP\n"); in ddr3_hw_training()
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H A Dddr3_pbs.c1 // SPDX-License-Identifier: GPL-2.0
70 * Desc: Execute the PBS TX phase.
92 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_tx()
102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx()
104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx()
105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx()
110 /* [0] = 1 - Enable SW override */ in ddr3_pbs_tx()
111 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx()
113 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx()
116 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_tx()
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/openbmc/u-boot/drivers/net/
H A Dmvneta.c1 // SPDX-License-Identifier: GPL-2.0
5 * U-Boot version:
6 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
30 #include <asm-generic/gpio.h>
148 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
150 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
220 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
252 /* Max number of Rx descriptors */
255 /* Max number of Tx descriptors */
[all …]
H A Dmvpp2.c8 * U-Boot version:
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
18 #include <dm/device-internal.h>
33 #include <asm-generic/gpio.h>
56 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
67 /* RX Fifo Registers */
309 /* TX Scheduler registers */
333 /* TX general registers */
346 /* Per-port registers */
392 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
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H A De1000.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
10 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
36 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
40 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
51 writel((value), ((a)->hw_addr + E1000_##reg))
53 readl((a)->hw_addr + E1000_##reg)
55 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
57 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
349 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
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/openbmc/u-boot/drivers/usb/gadget/
H A Daspeed_usbtty.c1 // SPDX-License-Identifier: GPL-2.0
121 /*-------------------------------------------------------------------------*/
123 __raw_readl(aspeed_udc->udc_base + (offset))
125 __raw_writel((u32)val, aspeed_udc->udc_base + (offset))
131 /*-------------------------------------------------------------------------*/
148 ep_reg = aspeed_udc->udc_base + AST_EP_BASE + in udc_stall_ep()
149 (AST_EP_OFFSET * (ep_num - 1)); in udc_stall_ep()
162 struct urb *urb = endpoint->tx_urb; in udc_endpoint_write()
171 return -1; in udc_endpoint_write()
174 ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; in udc_endpoint_write()
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/openbmc/qemu/hw/i3c/
H A Ddw-i3c.c7 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "qemu/error-report.h"
14 #include "hw/i3c/dw-i3c.h"
16 #include "hw/qdev-properties.h"
368 return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS); in dw_i3c_has_hdr_ts()
373 return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_DDR); in dw_i3c_has_hdr_ddr()
382 return ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_EN) && in dw_i3c_can_transmit()
383 !ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_RESUME); in dw_i3c_can_transmit()
388 uint8_t ibi_slice_size = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, in dw_i3c_ibi_slice_size()
410 bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); in dw_i3c_update_irq()
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