hw/i3c/dw-i3c: Add controller resets

Adds behavior to the device reset register.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Step

hw/i3c/dw-i3c: Add controller resets

Adds behavior to the device reset register.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-16-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c/dw-i3c: Add ctrl MMIO handling

Adds functionality to the CTRL register.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Patrick

hw/i3c/dw-i3c: Add ctrl MMIO handling

Adds functionality to the CTRL register.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-15-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c/dw-i3c: Add IBI handling

Adds handling for different IBI events that the controller can receive.
This includes:
- Handling a hot-join from a target
- Handling a secondary controller on the bu

hw/i3c/dw-i3c: Add IBI handling

Adds handling for different IBI events that the controller can receive.
This includes:
- Handling a hot-join from a target
- Handling a secondary controller on the bus requesting to be the
primary bus controller
- Handling an interrupt request from a target.

When receiving an IBI, the controller sets an interrupt to notify
software about what happened.
When the IBI is finished being serviced, the controller pushes the
result of the IBI and any data received from the target into the IBI
queue.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Stephen Longfield <slongfield@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-14-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c/dw-i3c: Add data TX and RX

This adds data and CCC transmission, reception, and the associated
queues required for data transmission and reception to happen.

The I3C controller transmits data

hw/i3c/dw-i3c: Add data TX and RX

This adds data and CCC transmission, reception, and the associated
queues required for data transmission and reception to happen.

The I3C controller transmits data by the user writing into a command
queue. When the queue has a command and an argument in it, the
controller starts executing the command.

The controller can execute 1 of 3 ways:
1. A larger data transfer that involves using the TX and RX queues. This
is the most common way the controller does transactions.

2. A small data transfer that involves sending a couple bytes passed
into the command queue argument.

3. An address assignment command. This is how the controller does
ENTDAA. When ENTDAA succeeds in assigning an address to a target, it
updates the controller's char table with the target's PID, BCR, and
DCR.

The controller determines what addresses to send by looking at the index
in the device address table specified by the argument in the command
queue. ENTDAA also uses these addresses to assign to targets on the bus.

When the controller is done executing a command, it puts a response in
the response queue indicating how command execution went.

In order for the user to send and receive data to/from the controller,
the user reads/writes to a bidirectional TX/RX port.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Stephen Longfield <slongfield@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-13-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c/dw-i3c: Add IRQ MMIO behavior

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Link: https://lore.k

hw/i3c/dw-i3c: Add IRQ MMIO behavior

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-12-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c/dw-i3c: Use 32 bits on MMIO writes

The registers are only 32 bits wide, so we should cast the 64-bit value
passed in to only be 32 bits wide.

Signed-off-by: Joe Komlodi <komlodi@google.com>

hw/i3c/dw-i3c: Use 32 bits on MMIO writes

The registers are only 32 bits wide, so we should cast the 64-bit value
passed in to only be 32 bits wide.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-11-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c/dw-i3c: Treat more registers as read-as-zero

RESET_CTRL and INTR_FORCE are write-only.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Link

hw/i3c/dw-i3c: Treat more registers as read-as-zero

RESET_CTRL and INTR_FORCE are write-only.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-10-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c/dw-i3c: Add register RO field masks

Adds read-only register masks for the DwC I3C controller.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.co

hw/i3c/dw-i3c: Add register RO field masks

Adds read-only register masks for the DwC I3C controller.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-9-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c/dw-i3c: Add more reset values

Adds reset values for the new registers added.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Link: https://

hw/i3c/dw-i3c: Add more reset values

Adds reset values for the new registers added.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-7-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c/dw-i3c: Add more register fields

Adds the rest of the Designware register fields.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Link: htt

hw/i3c/dw-i3c: Add more register fields

Adds the rest of the Designware register fields.

Signed-off-by: Joe Komlodi <komlodi@google.com>

Reviewed-by: Patrick Venture <venture@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-5-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/i3c: Split DesignWare I3C out of Aspeed I3C

The Aspeed I3C IP block is technically an Aspeed IP block that manages
6 DW I3C controllers.

To help reflect this better and to make it easier for oth

hw/i3c: Split DesignWare I3C out of Aspeed I3C

The Aspeed I3C IP block is technically an Aspeed IP block that manages
6 DW I3C controllers.

To help reflect this better and to make it easier for other SoCs to use
the DW I3C model, we'll split out the DW portion from the Aspeed
portion.

Signed-off-by: Joe Komlodi <komlodi@google.com>
Link: https://lore.kernel.org/qemu-devel/20250613000411.1516521-4-komlodi@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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