Lines Matching +full:tx +full:- +full:fifo +full:- +full:max +full:- +full:num

1 // SPDX-License-Identifier: GPL-2.0+
58 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
87 uint32_t hwcfg2 = readl(&regs->ghwcfg2); in init_fslspclksel()
97 clrsetbits_le32(&regs->host_regs.hcfg, in init_fslspclksel()
103 * Flush a Tx FIFO.
106 * @param num Tx FIFO to flush.
108 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) in dwc_otg_flush_tx_fifo() argument
112 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), in dwc_otg_flush_tx_fifo()
113 &regs->grstctl); in dwc_otg_flush_tx_fifo()
114 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, in dwc_otg_flush_tx_fifo()
124 * Flush Rx FIFO.
132 writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl); in dwc_otg_flush_rx_fifo()
133 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, in dwc_otg_flush_rx_fifo()
151 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, in dwc_otg_core_reset()
157 writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl); in dwc_otg_core_reset()
158 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, in dwc_otg_core_reset()
177 ret = device_get_supply_regulator(dev, "vbus-supply", in dwc_vbus_supply_init()
178 &priv->vbus_supply); in dwc_vbus_supply_init()
180 debug("%s: No vbus supply\n", dev->name); in dwc_vbus_supply_init()
184 ret = regulator_set_enable(priv->vbus_supply, true); in dwc_vbus_supply_init()
198 if (priv->vbus_supply) { in dwc_vbus_supply_exit()
199 ret = regulator_set_enable(priv->vbus_supply, false); in dwc_vbus_supply_exit()
226 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
243 writel(0, &regs->pcgcctl); in dwc_otg_core_host_init()
248 setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); in dwc_otg_core_host_init()
251 /* Configure data FIFO sizes */ in dwc_otg_core_host_init()
253 if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { in dwc_otg_core_host_init()
254 /* Rx FIFO */ in dwc_otg_core_host_init()
255 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz); in dwc_otg_core_host_init()
257 /* Non-periodic Tx FIFO */ in dwc_otg_core_host_init()
262 writel(nptxfifosize, &regs->gnptxfsiz); in dwc_otg_core_host_init()
264 /* Periodic Tx FIFO */ in dwc_otg_core_host_init()
270 writel(ptxfifosize, &regs->hptxfsiz); in dwc_otg_core_host_init()
275 clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); in dwc_otg_core_host_init()
278 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ in dwc_otg_core_host_init()
282 num_channels = readl(&regs->ghwcfg2); in dwc_otg_core_host_init()
288 clrsetbits_le32(&regs->hc_regs[i].hcchar, in dwc_otg_core_host_init()
294 clrsetbits_le32(&regs->hc_regs[i].hcchar, in dwc_otg_core_host_init()
297 ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar, in dwc_otg_core_host_init()
304 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { in dwc_otg_core_host_init()
305 hprt0 = readl(&regs->hprt0); in dwc_otg_core_host_init()
310 writel(hprt0, &regs->hprt0); in dwc_otg_core_host_init()
326 struct dwc2_core_regs *regs = priv->regs; in dwc_otg_core_init()
332 usbcfg = readl(&regs->gusbcfg); in dwc_otg_core_init()
335 if (priv->ext_vbus) { in dwc_otg_core_init()
337 if (!priv->oc_disable) { in dwc_otg_core_init()
351 writel(usbcfg, &regs->gusbcfg); in dwc_otg_core_init()
363 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL); in dwc_otg_core_init()
373 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) in dwc_otg_core_init()
378 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); in dwc_otg_core_init()
381 clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN | in dwc_otg_core_init()
384 setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN); in dwc_otg_core_init()
410 writel(usbcfg, &regs->gusbcfg); in dwc_otg_core_init()
416 usbcfg = readl(&regs->gusbcfg); in dwc_otg_core_init()
419 uint32_t hwcfg2 = readl(&regs->ghwcfg2); in dwc_otg_core_init()
429 if (priv->hnp_srp_disable) in dwc_otg_core_init()
432 writel(usbcfg, &regs->gusbcfg); in dwc_otg_core_init()
435 switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { in dwc_otg_core_init()
458 writel(ahbcfg, &regs->gahbcfg); in dwc_otg_core_init()
463 if (!priv->hnp_srp_disable) in dwc_otg_core_init()
469 setbits_le32(&regs->gusbcfg, usbcfg); in dwc_otg_core_init()
485 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num]; in dwc_otg_hc_init()
492 if (dev->speed == USB_SPEED_LOW) in dwc_otg_hc_init()
499 writel(hcchar, &hc_regs->hcchar); in dwc_otg_hc_init()
502 writel(0, &hc_regs->hcsplt); in dwc_otg_hc_init()
515 writel(hcsplt, &hc_regs->hcsplt); in dwc_otg_hc_init_split()
532 switch (cmd->requesttype & ~USB_DIR_IN) { in dwc_otg_submit_rh_msg_in_status()
547 hprt0 = readl(&regs->hprt0); in dwc_otg_submit_rh_msg_in_status()
583 dev->act_len = min(len, txlen); in dwc_otg_submit_rh_msg_in_status()
584 dev->status = stat; in dwc_otg_submit_rh_msg_in_status()
598 uint16_t wValue = cpu_to_le16(cmd->value); in dwc_otg_submit_rh_msg_in_descriptor()
599 uint16_t wLength = cpu_to_le16(cmd->length); in dwc_otg_submit_rh_msg_in_descriptor()
601 switch (cmd->requesttype & ~USB_DIR_IN) { in dwc_otg_submit_rh_msg_in_descriptor()
646 /* corresponds to data[4-7] */ in dwc_otg_submit_rh_msg_in_descriptor()
666 dev->act_len = min(len, txlen); in dwc_otg_submit_rh_msg_in_descriptor()
667 dev->status = stat; in dwc_otg_submit_rh_msg_in_descriptor()
680 switch (cmd->requesttype & ~USB_DIR_IN) { in dwc_otg_submit_rh_msg_in_configuration()
690 dev->act_len = min(len, txlen); in dwc_otg_submit_rh_msg_in_configuration()
691 dev->status = stat; in dwc_otg_submit_rh_msg_in_configuration()
701 switch (cmd->request) { in dwc_otg_submit_rh_msg_in()
703 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, in dwc_otg_submit_rh_msg_in()
723 struct dwc2_core_regs *regs = priv->regs; in dwc_otg_submit_rh_msg_out()
726 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); in dwc_otg_submit_rh_msg_out()
727 uint16_t wValue = cpu_to_le16(cmd->value); in dwc_otg_submit_rh_msg_out()
737 setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET); in dwc_otg_submit_rh_msg_out()
748 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | in dwc_otg_submit_rh_msg_out()
754 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST); in dwc_otg_submit_rh_msg_out()
758 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | in dwc_otg_submit_rh_msg_out()
770 priv->root_hub_devnum = wValue; in dwc_otg_submit_rh_msg_out()
781 dev->act_len = len; in dwc_otg_submit_rh_msg_out()
782 dev->status = stat; in dwc_otg_submit_rh_msg_out()
794 puts("Root-Hub submit IRQ: NOT implemented\n"); in dwc_otg_submit_rh_msg()
798 if (cmd->requesttype & USB_DIR_IN) in dwc_otg_submit_rh_msg()
813 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true, in wait_for_chhltd()
818 hcint = readl(&hc_regs->hcint); in wait_for_chhltd()
819 hctsiz = readl(&hc_regs->hctsiz); in wait_for_chhltd()
831 return -EAGAIN; in wait_for_chhltd()
834 return -EINVAL; in wait_for_chhltd()
857 &hc_regs->hctsiz); in transfer_chunk()
874 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); in transfer_chunk()
877 writel(0x3fff, &hc_regs->hcint); in transfer_chunk()
880 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | in transfer_chunk()
892 xfer_len -= sub; in transfer_chunk()
908 struct dwc2_core_regs *regs = priv->regs; in chunk_msg()
909 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL]; in chunk_msg()
910 struct dwc2_host_regs *host_regs = &regs->host_regs; in chunk_msg()
913 int max = usb_maxpacket(dev, pipe); in chunk_msg() local
928 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; in chunk_msg()
934 /* Make sure that max_xfer_len is a multiple of max packet size. */ in chunk_msg()
935 num_packets = max_xfer_len / max; in chunk_msg()
936 max_xfer_len = num_packets * max; in chunk_msg()
940 eptype, max); in chunk_msg()
943 if (dev->speed != USB_SPEED_HIGH) { in chunk_msg()
946 uint32_t hprt0 = readl(&regs->hprt0); in chunk_msg()
955 max_xfer_len = max; in chunk_msg()
963 xfer_len = len - done; in chunk_msg()
967 else if (xfer_len > max) in chunk_msg()
968 num_packets = (xfer_len + max - 1) / max; in chunk_msg()
973 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); in chunk_msg()
975 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); in chunk_msg()
978 int uframe_num = readl(&host_regs->hfnum); in chunk_msg()
983 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, in chunk_msg()
987 hcint = readl(&hc_regs->hcint); in chunk_msg()
993 readl(&host_regs->hfnum); in chunk_msg()
994 if (((frame_num - ssplit_frame_num) & in chunk_msg()
996 ret = -EAGAIN; in chunk_msg()
1002 readl(&host_regs->hfnum); in chunk_msg()
1022 writel(0, &hc_regs->hcintmsk); in chunk_msg()
1023 writel(0xFFFFFFFF, &hc_regs->hcint); in chunk_msg()
1025 dev->status = 0; in chunk_msg()
1026 dev->act_len = done; in chunk_msg()
1031 /* U-Boot USB transmission interface */
1039 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) { in _submit_bulk_msg()
1040 dev->status = 0; in _submit_bulk_msg()
1041 return -EINVAL; in _submit_bulk_msg()
1045 pid = &priv->in_data_toggle[devnum][ep]; in _submit_bulk_msg()
1047 pid = &priv->out_data_toggle[devnum][ep]; in _submit_bulk_msg()
1062 if (devnum == priv->root_hub_devnum) { in _submit_control_msg()
1063 dev->status = 0; in _submit_control_msg()
1064 dev->speed = USB_SPEED_HIGH; in _submit_control_msg()
1073 } while (ret == -EAGAIN); in _submit_control_msg()
1084 act_len += dev->act_len; in _submit_control_msg()
1085 buffer += dev->act_len; in _submit_control_msg()
1086 len -= dev->act_len; in _submit_control_msg()
1087 } while (ret == -EAGAIN); in _submit_control_msg()
1092 /* No-data CONTROL always ends with an IN transaction */ in _submit_control_msg()
1100 priv->status_buffer, 0); in _submit_control_msg()
1101 } while (ret == -EAGAIN); in _submit_control_msg()
1105 dev->act_len = act_len; in _submit_control_msg()
1122 return -ETIMEDOUT; in _submit_int_msg()
1125 if (ret != -EAGAIN) in _submit_int_msg()
1135 ret = reset_get_bulk(dev, &priv->resets); in dwc2_reset()
1141 if (ret == -ENOENT || ret == -ENOTSUPP) in dwc2_reset()
1147 ret = reset_deassert_bulk(&priv->resets); in dwc2_reset()
1149 reset_release_bulk(&priv->resets); in dwc2_reset()
1159 struct dwc2_core_regs *regs = priv->regs; in dwc2_init_common()
1168 snpsid = readl(&regs->gsnpsid); in dwc2_init_common()
1176 return -ENODEV; in dwc2_init_common()
1180 priv->ext_vbus = 1; in dwc2_init_common()
1182 priv->ext_vbus = 0; in dwc2_init_common()
1188 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | in dwc2_init_common()
1193 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | in dwc2_init_common()
1199 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0; in dwc2_init_common()
1200 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0; in dwc2_init_common()
1210 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) in dwc2_init_common()
1219 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | in dwc2_uninit_common()
1244 /* U-Boot USB control interface */
1250 priv->root_hub_devnum = 0; in usb_lowlevel_init()
1251 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; in usb_lowlevel_init()
1252 priv->aligned_buffer = aligned_buffer_addr; in usb_lowlevel_init()
1253 priv->status_buffer = status_buffer_addr; in usb_lowlevel_init()
1255 /* board-dependant init */ in usb_lowlevel_init()
1257 return -1; in usb_lowlevel_init()
1277 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, in dwc2_submit_control_msg()
1278 dev->name, udev, udev->dev->name, udev->portnr); in dwc2_submit_control_msg()
1288 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); in dwc2_submit_bulk_msg()
1299 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); in dwc2_submit_int_msg()
1311 return -EINVAL; in dwc2_usb_ofdata_to_platdata()
1312 priv->regs = (struct dwc2_core_regs *)addr; in dwc2_usb_ofdata_to_platdata()
1314 priv->oc_disable = dev_read_bool(dev, "disable-over-current"); in dwc2_usb_ofdata_to_platdata()
1315 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable"); in dwc2_usb_ofdata_to_platdata()
1325 bus_priv->desc_before_addr = true; in dwc2_usb_probe()
1339 dwc2_uninit_common(priv->regs); in dwc2_usb_remove()
1341 reset_release_bulk(&priv->resets); in dwc2_usb_remove()
1353 { .compatible = "brcm,bcm2835-usb" },
1354 { .compatible = "brcm,bcm2708-usb" },