Lines Matching +full:tx +full:- +full:fifo +full:- +full:max +full:- +full:num
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
112 uint32_t data = s->regs[IBEX_SPI_HOST_STATUS]; in ibex_spi_rxfifo_reset()
113 /* Empty the RX FIFO and assert RXEMPTY */ in ibex_spi_rxfifo_reset()
114 fifo8_reset(&s->rx_fifo); in ibex_spi_rxfifo_reset()
117 s->regs[IBEX_SPI_HOST_STATUS] = data; in ibex_spi_rxfifo_reset()
122 uint32_t data = s->regs[IBEX_SPI_HOST_STATUS]; in ibex_spi_txfifo_reset()
123 /* Empty the TX FIFO and assert TXEMPTY */ in ibex_spi_txfifo_reset()
124 fifo8_reset(&s->tx_fifo); in ibex_spi_txfifo_reset()
127 s->regs[IBEX_SPI_HOST_STATUS] = data; in ibex_spi_txfifo_reset()
136 s->regs[IBEX_SPI_HOST_INTR_STATE] = 0x00; in ibex_spi_host_reset()
137 s->regs[IBEX_SPI_HOST_INTR_ENABLE] = 0x00; in ibex_spi_host_reset()
138 s->regs[IBEX_SPI_HOST_INTR_TEST] = 0x00; in ibex_spi_host_reset()
139 s->regs[IBEX_SPI_HOST_ALERT_TEST] = 0x00; in ibex_spi_host_reset()
140 s->regs[IBEX_SPI_HOST_CONTROL] = 0x7f; in ibex_spi_host_reset()
141 s->regs[IBEX_SPI_HOST_STATUS] = 0x00; in ibex_spi_host_reset()
142 s->regs[IBEX_SPI_HOST_CONFIGOPTS] = 0x00; in ibex_spi_host_reset()
143 s->regs[IBEX_SPI_HOST_CSID] = 0x00; in ibex_spi_host_reset()
144 s->regs[IBEX_SPI_HOST_COMMAND] = 0x00; in ibex_spi_host_reset()
145 /* RX/TX Modelled by FIFO */ in ibex_spi_host_reset()
146 s->regs[IBEX_SPI_HOST_RXDATA] = 0x00; in ibex_spi_host_reset()
147 s->regs[IBEX_SPI_HOST_TXDATA] = 0x00; in ibex_spi_host_reset()
149 s->regs[IBEX_SPI_HOST_ERROR_ENABLE] = 0x1F; in ibex_spi_host_reset()
150 s->regs[IBEX_SPI_HOST_ERROR_STATUS] = 0x00; in ibex_spi_host_reset()
151 s->regs[IBEX_SPI_HOST_EVENT_ENABLE] = 0x00; in ibex_spi_host_reset()
156 s->init_status = true; in ibex_spi_host_reset()
169 uint32_t intr_test_reg = s->regs[IBEX_SPI_HOST_INTR_TEST]; in ibex_spi_host_irq()
170 uint32_t intr_en_reg = s->regs[IBEX_SPI_HOST_INTR_ENABLE]; in ibex_spi_host_irq()
171 uint32_t intr_state_reg = s->regs[IBEX_SPI_HOST_INTR_STATE]; in ibex_spi_host_irq()
173 uint32_t err_en_reg = s->regs[IBEX_SPI_HOST_ERROR_ENABLE]; in ibex_spi_host_irq()
174 uint32_t event_en_reg = s->regs[IBEX_SPI_HOST_EVENT_ENABLE]; in ibex_spi_host_irq()
175 uint32_t err_status_reg = s->regs[IBEX_SPI_HOST_ERROR_STATUS]; in ibex_spi_host_irq()
176 uint32_t status_reg = s->regs[IBEX_SPI_HOST_STATUS]; in ibex_spi_host_irq()
205 s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_ERROR_MASK; in ibex_spi_host_irq()
209 qemu_set_irq(s->host_err, err_irq); in ibex_spi_host_irq()
230 s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_SPI_EVENT_MASK; in ibex_spi_host_irq()
234 qemu_set_irq(s->event, event_irq); in ibex_spi_host_irq()
239 uint32_t rx, tx, data; in ibex_spi_host_transfer() local
240 /* Get num of one byte transfers */ in ibex_spi_host_transfer()
241 uint8_t segment_len = FIELD_EX32(s->regs[IBEX_SPI_HOST_COMMAND], in ibex_spi_host_transfer()
245 if (fifo8_is_empty(&s->tx_fifo)) { in ibex_spi_host_transfer()
247 s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXSTALL_MASK; in ibex_spi_host_transfer()
249 } else if (fifo8_is_full(&s->rx_fifo)) { in ibex_spi_host_transfer()
251 s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXSTALL_MASK; in ibex_spi_host_transfer()
254 tx = fifo8_pop(&s->tx_fifo); in ibex_spi_host_transfer()
257 rx = ssi_transfer(s->ssi, tx); in ibex_spi_host_transfer()
259 trace_ibex_spi_host_transfer(tx, rx); in ibex_spi_host_transfer()
261 if (!fifo8_is_full(&s->rx_fifo)) { in ibex_spi_host_transfer()
262 fifo8_push(&s->rx_fifo, rx); in ibex_spi_host_transfer()
265 s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXFULL_MASK; in ibex_spi_host_transfer()
267 --segment_len; in ibex_spi_host_transfer()
270 data = s->regs[IBEX_SPI_HOST_STATUS]; in ibex_spi_host_transfer()
276 data = FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / 4); in ibex_spi_host_transfer()
282 s->regs[IBEX_SPI_HOST_STATUS] = data; in ibex_spi_host_transfer()
304 rc = s->regs[addr]; in ibex_spi_host_read()
307 rc = s->regs[addr]; in ibex_spi_host_read()
310 rc = s->config_opts[s->regs[IBEX_SPI_HOST_CSID]]; in ibex_spi_host_read()
313 rc = s->regs[addr]; in ibex_spi_host_read()
317 s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXFULL_MASK; in ibex_spi_host_read()
320 if (fifo8_is_empty(&s->rx_fifo)) { in ibex_spi_host_read()
322 s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXEMPTY_MASK; in ibex_spi_host_read()
323 s->regs[IBEX_SPI_HOST_ERROR_STATUS] |= in ibex_spi_host_read()
327 rx_byte = fifo8_pop(&s->rx_fifo); in ibex_spi_host_read()
332 rc = s->regs[addr]; in ibex_spi_host_read()
365 s->regs[addr] = data; in ibex_spi_host_write()
368 s->regs[addr] = val32; in ibex_spi_host_write()
371 s->regs[addr] = val32; in ibex_spi_host_write()
375 s->regs[addr] = val32; in ibex_spi_host_write()
380 s->regs[addr] = val32; in ibex_spi_host_write()
385 s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_ACTIVE_MASK; in ibex_spi_host_write()
394 /* Update the respective config-opts register based on CSIDth index */ in ibex_spi_host_write()
395 s->config_opts[s->regs[IBEX_SPI_HOST_CSID]] = val32; in ibex_spi_host_write()
401 if (val32 >= s->num_cs) { in ibex_spi_host_write()
402 /* CSID exceeds max num_cs */ in ibex_spi_host_write()
403 s->regs[IBEX_SPI_HOST_ERROR_STATUS] |= in ibex_spi_host_write()
408 s->regs[addr] = val32; in ibex_spi_host_write()
411 s->regs[addr] = val32; in ibex_spi_host_write()
414 if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_CONTROL], in ibex_spi_host_write()
420 if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_STATUS], in ibex_spi_host_write()
422 s->regs[IBEX_SPI_HOST_ERROR_STATUS] |= R_ERROR_STATUS_CMDBUSY_MASK; in ibex_spi_host_write()
428 s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_READY_MASK; in ibex_spi_host_write()
432 "%s: Rx Only/Tx Only are not supported\n", __func__); in ibex_spi_host_write()
445 timer_mod(s->fifo_trigger_handle, in ibex_spi_host_write()
455 if (s->init_status) { in ibex_spi_host_write()
456 s->init_status = false; in ibex_spi_host_write()
462 if (fifo8_is_full(&s->tx_fifo)) { in ibex_spi_host_write()
464 s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXFULL_MASK; in ibex_spi_host_write()
465 s->regs[IBEX_SPI_HOST_ERROR_STATUS] |= in ibex_spi_host_write()
471 status = s->regs[IBEX_SPI_HOST_STATUS]; in ibex_spi_host_write()
481 fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8)); in ibex_spi_host_write()
483 status = s->regs[IBEX_SPI_HOST_STATUS]; in ibex_spi_host_write()
494 s->regs[IBEX_SPI_HOST_STATUS] = status; in ibex_spi_host_write()
497 s->regs[addr] = val32; in ibex_spi_host_write()
510 status = s->regs[addr]; in ibex_spi_host_write()
530 s->regs[addr] = status; in ibex_spi_host_write()
534 s->regs[addr] = val32; in ibex_spi_host_write()
594 s->ssi = ssi_create_bus(dev, "ssi"); in ibex_spi_host_realize()
595 s->cs_lines = g_new0(qemu_irq, s->num_cs); in ibex_spi_host_realize()
597 for (i = 0; i < s->num_cs; ++i) { in ibex_spi_host_realize()
598 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); in ibex_spi_host_realize()
601 /* Setup CONFIGOPTS Multi-register */ in ibex_spi_host_realize()
602 s->config_opts = g_new0(uint32_t, s->num_cs); in ibex_spi_host_realize()
604 /* Setup FIFO Interrupt Timer */ in ibex_spi_host_realize()
605 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, in ibex_spi_host_realize()
608 /* FIFO sizes as per OT Spec */ in ibex_spi_host_realize()
609 fifo8_create(&s->tx_fifo, IBEX_SPI_HOST_TXFIFO_LEN); in ibex_spi_host_realize()
610 fifo8_create(&s->rx_fifo, IBEX_SPI_HOST_RXFIFO_LEN); in ibex_spi_host_realize()
617 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->host_err); in ibex_spi_host_init()
618 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->event); in ibex_spi_host_init()
620 memory_region_init_io(&s->mmio, obj, &ibex_spi_ops, s, in ibex_spi_host_init()
622 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); in ibex_spi_host_init()
628 dc->realize = ibex_spi_host_realize; in ibex_spi_host_class_init()
630 dc->vmsd = &vmstate_ibex; in ibex_spi_host_class_init()