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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4";
10 io-width = <32>;
12 tRPab-min-tck = <3>;
13 tRCD-min-tck = <3>;
14 tWR-min-tck = <3>;
15 tRASmin-min-tck = <3>;
16 tRRD-min-tck = <2>;
17 tWTR-min-tck = <2>;
18 tXP-min-tck = <2>;
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
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H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dlpddr3_stock.c11 u8 tfaw = max(ns_to_t(50), 4); in mctl_set_timing_params()
12 u8 trrd = max(ns_to_t(10), 2); in mctl_set_timing_params()
13 u8 trcd = max(ns_to_t(24), 2); in mctl_set_timing_params()
15 u8 txp = max(ns_to_t(8), 2); in mctl_set_timing_params()
16 u8 twtr = max(ns_to_t(8), 2); in mctl_set_timing_params()
17 u8 trtp = max(ns_to_t(8), 2); in mctl_set_timing_params()
18 u8 twr = max(ns_to_t(15), 3); in mctl_set_timing_params()
19 u8 trp = max(ns_to_t(27), 2); in mctl_set_timing_params()
20 u8 tras = ns_to_t(42); in mctl_set_timing_params() local
39 u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ in mctl_set_timing_params()
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H A Dddr2_v3s.c12 u8 trrd = max(ns_to_t(10), 2); in mctl_set_timing_params()
16 u8 twtr = max(ns_to_t(8), 2); in mctl_set_timing_params()
17 u8 trtp = max(ns_to_t(8), 2); in mctl_set_timing_params()
18 u8 twr = max(ns_to_t(15), 3); in mctl_set_timing_params()
20 u8 tras = ns_to_t(45); in mctl_set_timing_params() local
39 u32 tdinit1 = (500 * CONFIG_DRAM_CLK) / 1000 + 1; /* 500ns */ in mctl_set_timing_params()
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
48 writel(0x263, &mctl_ctl->mr[0]); in mctl_set_timing_params()
49 writel(0x4, &mctl_ctl->mr[1]); in mctl_set_timing_params()
50 writel(0x0, &mctl_ctl->mr[2]); in mctl_set_timing_params()
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H A Dddr3_1333.c12 u8 trrd = max(ns_to_t(10), 4); in mctl_set_timing_params()
15 u8 txp = max(ns_to_t(8), 3); in mctl_set_timing_params()
16 u8 twtr = max(ns_to_t(8), 4); in mctl_set_timing_params()
17 u8 trtp = max(ns_to_t(8), 4); in mctl_set_timing_params()
18 u8 twr = max(ns_to_t(15), 3); in mctl_set_timing_params()
20 u8 tras = ns_to_t(38); in mctl_set_timing_params() local
39 u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ in mctl_set_timing_params()
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
48 writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ in mctl_set_timing_params()
49 writel(0x40, &mctl_ctl->mr[1]); in mctl_set_timing_params()
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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015
10 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
26 * Allwinner as part of the open-source bootloader release (refer to
27 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
36 * Note that the Zynq-documentation provides a very close match for the DDR
42 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
48 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
50 * 2) Only 2T-mode has been implemented and tested.
62 * The driver should be driven from a device-tree based configuration that
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H A Ddram_sun8i_a83t.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015 Allwinner Technology Co.
36 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
37 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | in mctl_set_cr()
38 (para->seq ? MCTL_CR_SEQUENCE : 0) | in mctl_set_cr()
39 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
40 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_set_cr()
41 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
42 &mctl_com->cr); in mctl_set_cr()
47 u8 orig_rank = para->rank; in auto_detect_dram_size()
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H A Ddram_sun8i_a33.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015 Allwinner Technology Co.
17 /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
37 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
39 (para->seq ? MCTL_CR_SEQUENCE : 0) | in mctl_set_cr()
40 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
41 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_set_cr()
42 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
43 &mctl_com->cr); in mctl_set_cr()
48 u8 orig_rank = para->rank; in auto_detect_dram_size()
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H A Ddram_sun50i_h6.c6 * SPDX-License-Identifier: GPL-2.0+
21 * COM is allwinner-specific. On H6, the address mapping function is moved
31 * not seen on other SoCs in U-Boot. The only SoC that is also known to have
38 * the 32-bit wide access consists of. Also three control signals can be
68 switch (para->type) { in mctl_core_init()
83 writel(val | BIT(0), &mctl_phy->pir); in mctl_phy_pir_init()
84 mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0)); in mctl_phy_pir_init()
136 writel(cfg0, &mctl_com->master[port].cfg0); in mbus_configure_port()
137 writel(cfg1, &mctl_com->master[port].cfg1); in mbus_configure_port()
150 writel(399, &mctl_com->tmr); in mctl_set_master_priority()
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/openbmc/linux/drivers/memory/
H A Dof_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * of_get_min_tck() - extract min timing values for ddr
38 ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); in of_get_min_tck()
39 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_get_min_tck()
40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
41 ret |= of_property_read_u32(np, "tRASmin-min-tck", &min->tRASmin); in of_get_min_tck()
42 ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD); in of_get_min_tck()
43 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_get_min_tck()
44 ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP); in of_get_min_tck()
45 ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP); in of_get_min_tck()
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/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmem.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2008
5 * Richard Woodruff <r-woodruff2@ti.com>
38 * counter is a result of ( tREFI / tCK ) - 50.
41 #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
42 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
43 #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
52 /* rkw - need to find of 90/72 degree recommendation for speed like before */
66 #define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ argument
69 ACTIM_CTRLA_TRAS(tras) | \
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/openbmc/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
108 * CWL = 5 if tCK >= 2.5ns
109 * 6 if 2.5ns > tCK >= 1.875ns
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/openbmc/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/devfreq-event.h>
100 * struct dmc_opp_table - Operating level desciption
112 * struct exynos5_dmc - main structure describing DMC device
143 * @last_overflow_ts: time (in ns) of last overflow of each DREX
195 __val = (t_val) << (timing)->bit_beg; \
212 TIMING_FIELD("tRAS", 0, 5),
219 TIMING_FIELD("tW2W-C2C", 14, 14),
220 TIMING_FIELD("tR2R-C2C", 12, 12),
242 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
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/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * EC1. Modify DQIDLY and DQSI-MCLK2X calibration algorithm
28 * EC6. Remove AST2300-A0 PCI-e workaround
31 * EC9. Add DRAM size auto-detection
36 * EC1. Add solution of LPC lock issue due to watchdog reset. (AP note A2300-11)
63 * EC1. Default assign X-DMA engine to VGA memory domain, MCR08[16] = 1.
67 * CONFIG_DRAM_336 // 336MHz (DDR-667)
68 * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
145 cmp r3, r2, lsr #8 @ record max
159 cmp r3, r2, lsr #24 @ record max
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/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspd_sdram.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
8 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
28 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info()
31 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) in board_add_ram_info()
32 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); in board_add_ram_info()
35 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info()
36 puts(", 16-bit"); in board_add_ram_info()
37 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info()
38 puts(", 32-bit"); in board_add_ram_info()
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/openbmc/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/memory/rk3368-dmc.h>
10 #include <dt-structs.h>
123 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
125 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
133 (((n - 5) & 0x7) << 3)
141 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
143 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
149 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
151 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
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/openbmc/linux/sound/pci/asihpi/
H A Dhpi6000.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 1997-2011 AudioScience Inc. <support@audioscience.com>
18 (C) Copyright AudioScience Inc. 1998-2003
78 /* can't access SDRAM - test#1 */
80 /* can't access SDRAM - test#2 */
210 switch (phm->function) { in subsys_message()
215 phr->error = HPI_ERROR_INVALID_FUNC; in subsys_message()
223 struct hpi_hw_obj *phw = pao->priv; in control_message()
225 switch (phm->function) { in control_message()
227 if (pao->has_control_cache) { in control_message()
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H A Dhpi6205.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 1997-2014 AudioScience Inc. <support@audioscience.com>
17 (C) Copyright AudioScience Inc. 1998-2010
61 /* Host-to-DSP Control Register (HDCR) bitfields */
70 * BAR1 maps to non-prefetchable 8 Mbyte memory block
114 /* a non-NULL handle means there is an HPI allocated buffer */
117 /* non-zero size means a buffer exists, may be external */
224 switch (phm->function) { in subsys_message()
229 phr->error = HPI_ERROR_INVALID_FUNC; in subsys_message()
238 struct hpi_hw_obj *phw = pao->priv; in control_message()
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/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datomfirmware.h6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
656 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
657 …eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without A…
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H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.c1 // SPDX-License-Identifier: Intel
66 uint8_t trp, trcd, tras, twr, twtr, trrd, trtp, tfaw; in prog_ddr_timing_control() local
82 tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */ in prog_ddr_timing_control()
83 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
86 tras = MCEIL(mrc_params->params.ras, tck); in prog_ddr_timing_control()
88 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in prog_ddr_timing_control()
91 twtr = MCEIL(mrc_params->params.wtr, tck); in prog_ddr_timing_control()
92 trrd = MCEIL(mrc_params->params.rrd, tck); in prog_ddr_timing_control()
94 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
96 wl = 5 + mrc_params->ddr_speed; in prog_ddr_timing_control()
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/openbmc/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
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