Lines Matching +full:tras +full:- +full:max +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015 Allwinner Technology Co.
36 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
37 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | in mctl_set_cr()
38 (para->seq ? MCTL_CR_SEQUENCE : 0) | in mctl_set_cr()
39 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
40 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_set_cr()
41 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
42 &mctl_com->cr); in mctl_set_cr()
47 u8 orig_rank = para->rank; in auto_detect_dram_size()
51 para->page_size = 512; in auto_detect_dram_size()
52 para->seq = 1; in auto_detect_dram_size()
53 para->rows = 16; in auto_detect_dram_size()
54 para->rank = 1; in auto_detect_dram_size()
57 if (mctl_mem_matches(1 << (rows + 9))) /* row-column */ in auto_detect_dram_size()
62 para->rows = 11; in auto_detect_dram_size()
63 para->page_size = 8192; in auto_detect_dram_size()
70 para->seq = 0; in auto_detect_dram_size()
71 para->rank = orig_rank; in auto_detect_dram_size()
72 para->rows = rows; in auto_detect_dram_size()
73 para->page_size = 1 << columns; in auto_detect_dram_size()
94 u8 trrd = max(ns_to_t(10), 4); in auto_set_timing_para()
97 u8 txp = max(ns_to_t(8), 3); in auto_set_timing_para()
98 u8 twtr = max(ns_to_t(8), 4); in auto_set_timing_para()
99 u8 trtp = max(ns_to_t(8), 4); in auto_set_timing_para()
100 u8 twr = max(ns_to_t(15), 3); in auto_set_timing_para()
102 u8 tras = ns_to_t(38); in auto_set_timing_para() local
122 u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */ in auto_set_timing_para()
128 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
133 if (para->dram_type == DRAM_TYPE_DDR3) { in auto_set_timing_para()
134 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
135 writel(MCTL_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
136 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
137 writel(MCTL_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
138 } else if (para->dram_type == DRAM_TYPE_LPDDR3) { in auto_set_timing_para()
139 writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
140 writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
141 writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
142 writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
145 tfaw = max(ns_to_t(50), 4); in auto_set_timing_para()
146 trrd = max(ns_to_t(10), 2); in auto_set_timing_para()
147 trcd = max(ns_to_t(24), 2); in auto_set_timing_para()
149 txp = max(ns_to_t(8), 2); in auto_set_timing_para()
150 twtr = max(ns_to_t(8), 2); in auto_set_timing_para()
151 trtp = max(ns_to_t(8), 2); in auto_set_timing_para()
152 trp = max(ns_to_t(27), 2); in auto_set_timing_para()
153 tras = ns_to_t(42); in auto_set_timing_para()
162 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ in auto_set_timing_para()
167 trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
170 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
171 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
173 writel(reg_val, &mctl_ctl->dramtmg1); in auto_set_timing_para()
175 writel(reg_val, &mctl_ctl->dramtmg2); in auto_set_timing_para()
177 writel(reg_val, &mctl_ctl->dramtmg3); in auto_set_timing_para()
179 writel(reg_val, &mctl_ctl->dramtmg4); in auto_set_timing_para()
181 writel(reg_val, &mctl_ctl->dramtmg5); in auto_set_timing_para()
182 /* Set two rank timing and exit self-refresh timing */ in auto_set_timing_para()
183 reg_val = readl(&mctl_ctl->dramtmg8); in auto_set_timing_para()
188 writel(reg_val, &mctl_ctl->dramtmg8); in auto_set_timing_para()
193 writel(reg_val, &mctl_ctl->pitmg0); in auto_set_timing_para()
194 /* Set phy time PTR0-2 use default */ in auto_set_timing_para()
195 writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); in auto_set_timing_para()
196 writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4); in auto_set_timing_para()
199 writel(reg_val, &mctl_ctl->rfshtmg); in auto_set_timing_para()
207 writel(val, &mctl_ctl->pir); in mctl_set_pir()
208 mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1); in mctl_set_pir()
216 if (para->rank == 2) in mctl_data_train_cfg()
217 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); in mctl_data_train_cfg()
219 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); in mctl_data_train_cfg()
230 return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; in mctl_train_dram()
263 u32 low_data_lines_status; /* Training status of datalines 0 - 7 */ in mctl_channel_init()
264 u32 high_data_lines_status; /* Training status of datalines 8 - 15 */ in mctl_channel_init()
270 writel(0x000101a0, &mctl_com->bwcr); in mctl_channel_init()
272 writel(0x1, &mctl_com->mapr); in mctl_channel_init()
277 clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30); in mctl_channel_init()
278 clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26); in mctl_channel_init()
309 setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19); in mctl_channel_init()
311 setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19); in mctl_channel_init()
313 /* Auto detect dram config, set 2 rank and 16bit bus-width */ in mctl_channel_init()
314 para->cs1 = 0; in mctl_channel_init()
315 para->rank = 2; in mctl_channel_init()
316 para->bus_width = 16; in mctl_channel_init()
320 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); in mctl_channel_init()
321 clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); in mctl_channel_init()
323 if (para->dram_type == DRAM_TYPE_LPDDR3) in mctl_channel_init()
324 clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) , in mctl_channel_init()
326 if (readl(&mctl_com->cr) & 0x1) in mctl_channel_init()
327 writel(0x00000303, &mctl_ctl->odtmap); in mctl_channel_init()
329 writel(0x00000201, &mctl_ctl->odtmap); in mctl_channel_init()
337 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
348 return -EIO; in mctl_channel_init()
351 para->rank = 1; in mctl_channel_init()
358 /* Retry 16 bit bus-width with CS1 set */ in mctl_channel_init()
359 para->cs1 = 1; in mctl_channel_init()
365 /* Try 8 bit bus-width */ in mctl_channel_init()
367 para->cs1 = 0; in mctl_channel_init()
368 para->bus_width = 8; in mctl_channel_init()
371 return -EIO; in mctl_channel_init()
375 mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); in mctl_channel_init()
378 setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); in mctl_channel_init()
381 writel(0x00aa0060, &mctl_ctl->pgcr3); in mctl_channel_init()
383 writel(0xffffffff, &mctl_com->maer); in mctl_channel_init()
395 clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
396 clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
397 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
398 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
399 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
401 clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31); in mctl_sys_init()
405 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, in mctl_sys_init()
408 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
410 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
411 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
412 setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
413 setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
415 para->rank = 2; in mctl_sys_init()
416 para->bus_width = 16; in mctl_sys_init()
420 writel(0x0000e00f, &mctl_ctl->clken); /* normal */ in mctl_sys_init()
461 writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); in sunxi_dram_init()
465 writel(0x00000303, &mctl_ctl->odtmap); in sunxi_dram_init()
467 writel(0x00000201, &mctl_ctl->odtmap); in sunxi_dram_init()