Lines Matching +full:tras +full:- +full:max +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
8 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
28 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info()
31 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) in board_add_ram_info()
32 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); in board_add_ram_info()
35 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info()
36 puts(", 16-bit"); in board_add_ram_info()
37 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info()
38 puts(", 32-bit"); in board_add_ram_info()
42 if (ddr->sdram_cfg & SDRAM_CFG_32_BE) in board_add_ram_info()
43 puts(", 32-bit"); in board_add_ram_info()
45 puts(", 64-bit"); in board_add_ram_info()
48 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) in board_add_ram_info()
53 printf(", %s MHz)", strmhz(buf, gd->mem_clk)); in board_add_ram_info()
81 mem_bus_clk = gd->mem_clk >> 1; in picos_to_clk()
103 printf ("\nDIMM type: %-18.18s\n", spd->mpart); in spd_debug()
104 printf ("SPD size: %d\n", spd->info_size); in spd_debug()
105 printf ("EEPROM size: %d\n", 1 << spd->chip_size); in spd_debug()
106 printf ("Memory type: %d\n", spd->mem_type); in spd_debug()
107 printf ("Row addr: %d\n", spd->nrow_addr); in spd_debug()
108 printf ("Column addr: %d\n", spd->ncol_addr); in spd_debug()
109 printf ("# of rows: %d\n", spd->nrows); in spd_debug()
110 printf ("Row density: %d\n", spd->row_dens); in spd_debug()
111 printf ("# of banks: %d\n", spd->nbanks); in spd_debug()
113 256 * spd->dataw_msb + spd->dataw_lsb); in spd_debug()
114 printf ("Chip width: %d\n", spd->primw); in spd_debug()
115 printf ("Refresh rate: %02X\n", spd->refresh); in spd_debug()
116 printf ("CAS latencies: %02X\n", spd->cas_lat); in spd_debug()
117 printf ("Write latencies: %02X\n", spd->write_lat); in spd_debug()
118 printf ("tRP: %d\n", spd->trp); in spd_debug()
119 printf ("tRCD: %d\n", spd->trcd); in spd_debug()
127 volatile ddr83xx_t *ddr = &immap->ddr; in spd_sdram()
128 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; in spd_sdram()
158 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0); in spd_sdram()
205 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; in spd_sdram()
221 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; in spd_sdram()
222 ddr->cs_config[0] = ( 1 << 31 in spd_sdram()
226 | ((spd.nrow_addr - 12) << 8) in spd_sdram()
227 | (spd.ncol_addr - 8) ); in spd_sdram()
229 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); in spd_sdram()
230 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); in spd_sdram()
233 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) in spd_sdram()
234 | ((banksize(spd.row_dens) >> 23) - 1) ); in spd_sdram()
235 ddr->cs_config[1] = ( 1<<31 in spd_sdram()
239 | ((spd.nrow_addr - 12) << 8) in spd_sdram()
240 | (spd.ncol_addr - 8) ); in spd_sdram()
241 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); in spd_sdram()
242 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); in spd_sdram()
246 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; in spd_sdram()
247 ddr->cs_config[2] = ( 1 << 31 in spd_sdram()
251 | ((spd.nrow_addr - 12) << 8) in spd_sdram()
252 | (spd.ncol_addr - 8) ); in spd_sdram()
254 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); in spd_sdram()
255 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); in spd_sdram()
258 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) in spd_sdram()
259 | ((banksize(spd.row_dens) >> 23) - 1) ); in spd_sdram()
260 ddr->cs_config[3] = ( 1<<31 in spd_sdram()
264 | ((spd.nrow_addr - 12) << 8) in spd_sdram()
265 | (spd.ncol_addr - 8) ); in spd_sdram()
266 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); in spd_sdram()
267 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); in spd_sdram()
284 ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in spd_sdram()
285 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); in spd_sdram()
286 debug("DDR:bar=0x%08x\n", ecm->bar); in spd_sdram()
287 debug("DDR:ar=0x%08x\n", ecm->ar); in spd_sdram()
296 * ------- ------- ------- ----- in spd_sdram()
326 ddrc_clk = gd->mem_clk / 1000000; in spd_sdram()
329 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */ in spd_sdram()
345 effective_data_rate = 400; /* 5ns */ in spd_sdram()
349 effective_data_rate = 333; /* 6ns */ in spd_sdram()
351 caslat = caslat - 1; in spd_sdram()
356 effective_data_rate = 266; /* 7.5ns */ in spd_sdram()
358 caslat = caslat - 2; in spd_sdram()
360 caslat = caslat - 1; in spd_sdram()
365 effective_data_rate = 200; /* 10ns */ in spd_sdram()
367 caslat = caslat - 2; in spd_sdram()
369 caslat = caslat - 1; in spd_sdram()
376 effective_data_rate = 333; /* 6ns */ in spd_sdram()
380 effective_data_rate = 266; /* 7.5ns */ in spd_sdram()
382 caslat = caslat - 1; in spd_sdram()
387 effective_data_rate = 200; /* 10ns */ in spd_sdram()
389 caslat = caslat - 2; in spd_sdram()
391 caslat = caslat - 1; in spd_sdram()
399 "max data rate of the module\n"); in spd_sdram()
403 effective_data_rate = 266; /* 7.5ns */ in spd_sdram()
407 effective_data_rate = 200; /* 10ns */ in spd_sdram()
409 caslat = caslat - 1; in spd_sdram()
415 "max data rate of the module\n"); in spd_sdram()
419 effective_data_rate = 200; /* 10ns */ in spd_sdram()
433 ddr->debug_reg = 0x201c0000; /* CL=2 */ in spd_sdram()
435 ddr->debug_reg = 0x202c0000; /* CL=2.5 */ in spd_sdram()
437 ddr->debug_reg = 0x202c0000; /* CL=3.0 */ in spd_sdram()
441 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); in spd_sdram()
446 * Force caslat_ctrl to be DDR Controller field-sized. in spd_sdram()
451 caslat_ctrl = (2 * caslat - 1) & 0x0f; in spd_sdram()
468 ddr->timing_cfg_0 = (0 in spd_sdram()
474 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in spd_sdram()
495 * DDR I: Byte 42 straight up in ns. in spd_sdram()
496 * DDR II: Byte 40 and 42 swizzled some, in ns. in spd_sdram()
524 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the in spd_sdram()
529 trfc_low = (trfc_clk - 8) & 0xf; in spd_sdram()
531 ddr->timing_cfg_1 = in spd_sdram()
533 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */ in spd_sdram()
553 add_lat = 4 - caslat; in spd_sdram()
589 wr_lat = caslat - 1; in spd_sdram()
602 * Empirically set ~MCAS-to-preamble override for DDR 2. in spd_sdram()
623 ddr->timing_cfg_2 = (0 in spd_sdram()
633 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); in spd_sdram()
634 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); in spd_sdram()
660 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */ in spd_sdram()
663 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */ in spd_sdram()
666 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */ in spd_sdram()
669 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */ in spd_sdram()
686 ddr->sdram_mode = in spd_sdram()
694 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */ in spd_sdram()
699 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); in spd_sdram()
704 ddr->sdram_mode2 = 0; in spd_sdram()
705 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2); in spd_sdram()
739 * If auto-charge is used, set BSTOPRE = 0 in spd_sdram()
741 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100; in spd_sdram()
742 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); in spd_sdram()
754 ddr->sdram_cfg2 = (0 in spd_sdram()
760 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); in spd_sdram()
764 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in spd_sdram()
766 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); in spd_sdram()
779 * sdram_cfg[1] = 1 (self-refresh-enable) in spd_sdram()
784 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts) in spd_sdram()
797 /* sdram_cfg[3] = RD_EN - registered DIMM enable */ in spd_sdram()
817 ddr->err_disable = ~ECC_ERROR_ENABLE; in spd_sdram()
820 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | in spd_sdram()
824 debug("DDR:err_disable=0x%08x\n", ddr->err_disable); in spd_sdram()
825 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); in spd_sdram()
836 ddr->sdram_cfg = sdram_cfg; in spd_sdram()
840 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); in spd_sdram()
881 volatile ddr83xx_t *ddr= &immap->ddr; in ddr_enable_ecc()
907 debug("ddr init duration: %ld ms\n", t_end - t_start); in ddr_enable_ecc()
910 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME) in ddr_enable_ecc()
911 ddr->err_detect |= ECC_ERROR_DETECT_MME; in ddr_enable_ecc()
912 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE) in ddr_enable_ecc()
913 ddr->err_detect |= ECC_ERROR_DETECT_MBE; in ddr_enable_ecc()
914 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE) in ddr_enable_ecc()
915 ddr->err_detect |= ECC_ERROR_DETECT_SBE; in ddr_enable_ecc()
916 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE) in ddr_enable_ecc()
917 ddr->err_detect |= ECC_ERROR_DETECT_MSE; in ddr_enable_ecc()
919 /* Disable ECC-Interrupts */ in ddr_enable_ecc()
920 ddr->err_int_en &= ECC_ERR_INT_DISABLE; in ddr_enable_ecc()
923 ddr->err_disable &= ECC_ERROR_ENABLE; in ddr_enable_ecc()