6  * SPDX-License-Identifier:	GPL-2.0+
21  * COM is allwinner-specific. On H6, the address mapping function is moved
31  * not seen on other SoCs in U-Boot. The only SoC that is also known to have
38  * the 32-bit wide access consists of. Also three control signals can be
68 	switch (para->type) {  in mctl_core_init()
83 	writel(val | BIT(0), &mctl_phy->pir);  in mctl_phy_pir_init()
84 	mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));  in mctl_phy_pir_init()
136 	writel(cfg0, &mctl_com->master[port].cfg0);  in mbus_configure_port()
137 	writel(cfg1, &mctl_com->master[port].cfg1);  in mbus_configure_port()
150 	writel(399, &mctl_com->tmr);  in mctl_set_master_priority()
151 	writel(BIT(16), &mctl_com->bwcr);  in mctl_set_master_priority()
187 	u8 tfaw		= max(ns_to_t(50), 4);  in mctl_set_timing_lpddr3()
188 	u8 trrd		= max(ns_to_t(10), 2);  in mctl_set_timing_lpddr3()
189 	u8 trcd		= max(ns_to_t(24), 2);  in mctl_set_timing_lpddr3()
191 	u8 txp		= max(ns_to_t(8), 2);  in mctl_set_timing_lpddr3()
192 	u8 twtr		= max(ns_to_t(8), 2);  in mctl_set_timing_lpddr3()
193 	u8 trtp		= max(ns_to_t(8), 2);  in mctl_set_timing_lpddr3()
194 	u8 twr		= max(ns_to_t(15), 2);  in mctl_set_timing_lpddr3()
196 	u8 tras		= ns_to_t(42);  in mctl_set_timing_lpddr3()  local
227 	u32 tdinit1	= (100 * CONFIG_DRAM_CLK) / 1000 + 1;	/* 100ns */  in mctl_set_timing_lpddr3()
238 	u8 trd2wr	= tcl + 4 + (tcksrea >> 1) - tcwl + 1;  in mctl_set_timing_lpddr3()
241 	memcpy(mctl_phy->mr, mr_lpddr3, sizeof(mr_lpddr3));  in mctl_set_timing_lpddr3()
244 	writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,  in mctl_set_timing_lpddr3()
245 	       &mctl_ctl->dramtmg[0]);  in mctl_set_timing_lpddr3()
246 	writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);  in mctl_set_timing_lpddr3()
248 	       &mctl_ctl->dramtmg[2]);  in mctl_set_timing_lpddr3()
249 	writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);  in mctl_set_timing_lpddr3()
251 	       &mctl_ctl->dramtmg[4]);  in mctl_set_timing_lpddr3()
253 	       &mctl_ctl->dramtmg[5]);  in mctl_set_timing_lpddr3()
255 	writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);  in mctl_set_timing_lpddr3()
257 	       &mctl_ctl->dramtmg[8]);  in mctl_set_timing_lpddr3()
258 	writel(txsr, &mctl_ctl->dramtmg[14]);  in mctl_set_timing_lpddr3()
260 	clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));  in mctl_set_timing_lpddr3()
261 	writel(0, &mctl_ctl->dfimisc);  in mctl_set_timing_lpddr3()
262 	clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);  in mctl_set_timing_lpddr3()
268 	writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),  in mctl_set_timing_lpddr3()
269 	       &mctl_phy->dtpr[0]);  in mctl_set_timing_lpddr3()
270 	writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);  in mctl_set_timing_lpddr3()
271 	writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);  in mctl_set_timing_lpddr3()
272 	writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),  in mctl_set_timing_lpddr3()
273 	       &mctl_phy->dtpr[3]);  in mctl_set_timing_lpddr3()
274 	writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);  in mctl_set_timing_lpddr3()
275 	writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);  in mctl_set_timing_lpddr3()
276 	writel(0x0505, &mctl_phy->dtpr[6]);  in mctl_set_timing_lpddr3()
280 	       &mctl_ctl->dfitmg0);  in mctl_set_timing_lpddr3()
281 	writel(0x040201, &mctl_ctl->dfitmg1);  in mctl_set_timing_lpddr3()
284 	writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);  in mctl_set_timing_lpddr3()
285 	writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);  in mctl_set_timing_lpddr3()
288 	writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);  in mctl_set_timing_lpddr3()
300 	/* Put all DRAM-related blocks to reset state */  in mctl_sys_init()
301 	clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);  in mctl_sys_init()
302 	clrbits_le32(&ccm->dram_gate_reset, BIT(0));  in mctl_sys_init()
304 	writel(0, &ccm->dram_gate_reset);  in mctl_sys_init()
305 	clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);  in mctl_sys_init()
306 	clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);  in mctl_sys_init()
312 	       CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);  in mctl_sys_init()
313 	mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);  in mctl_sys_init()
316 	writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);  in mctl_sys_init()
317 	setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);  in mctl_sys_init()
318 	writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);  in mctl_sys_init()
320 	setbits_le32(&ccm->dram_gate_reset, BIT(0));  in mctl_sys_init()
323 	writel(0, &mctl_com->maer0);  in mctl_sys_init()
324 	writel(0, &mctl_com->maer1);  in mctl_sys_init()
325 	writel(0, &mctl_com->maer2);  in mctl_sys_init()
328 	setbits_le32(&ccm->mbus_cfg, MBUS_RESET);  in mctl_sys_init()
329 	setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);  in mctl_sys_init()
330 	setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);  in mctl_sys_init()
334 	writel(0x8000, &mctl_ctl->unk_0x00c);  in mctl_sys_init()
341 	u8 cols = para->cols;  in mctl_set_addrmap()
342 	u8 rows = para->rows;  in mctl_set_addrmap()
343 	u8 ranks = para->ranks;  in mctl_set_addrmap()
347 		mctl_ctl->addrmap[0] = rows + cols - 3;  in mctl_set_addrmap()
349 		mctl_ctl->addrmap[0] = 0x1F;  in mctl_set_addrmap()
352 	mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;  in mctl_set_addrmap()
355 	mctl_ctl->addrmap[2] = 0;  in mctl_set_addrmap()
358 		mctl_ctl->addrmap[3] = 0x1F1F0000;  in mctl_set_addrmap()
359 		mctl_ctl->addrmap[4] = 0x1F1F;  in mctl_set_addrmap()
362 		mctl_ctl->addrmap[3] = 0x1F000000;  in mctl_set_addrmap()
363 		mctl_ctl->addrmap[4] = 0x1F1F;  in mctl_set_addrmap()
366 		mctl_ctl->addrmap[3] = 0;  in mctl_set_addrmap()
367 		mctl_ctl->addrmap[4] = 0x1F1F;  in mctl_set_addrmap()
370 		mctl_ctl->addrmap[3] = 0;  in mctl_set_addrmap()
371 		mctl_ctl->addrmap[4] = 0x1F00;  in mctl_set_addrmap()
374 		mctl_ctl->addrmap[3] = 0;  in mctl_set_addrmap()
375 		mctl_ctl->addrmap[4] = 0;  in mctl_set_addrmap()
382 	mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);  in mctl_set_addrmap()
385 		mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;  in mctl_set_addrmap()
386 		mctl_ctl->addrmap[7] = 0x0F0F;  in mctl_set_addrmap()
389 		mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;  in mctl_set_addrmap()
390 		mctl_ctl->addrmap[7] = 0x0F0F;  in mctl_set_addrmap()
393 		mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;  in mctl_set_addrmap()
394 		mctl_ctl->addrmap[7] = 0x0F0F;  in mctl_set_addrmap()
397 		mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);  in mctl_set_addrmap()
398 		mctl_ctl->addrmap[7] = 0x0F0F;  in mctl_set_addrmap()
401 		mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);  in mctl_set_addrmap()
402 		mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;  in mctl_set_addrmap()
405 		mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);  in mctl_set_addrmap()
406 		mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);  in mctl_set_addrmap()
413 	mctl_ctl->addrmap[8] = 0x3F3F;  in mctl_set_addrmap()
428 	setbits_le32(&mctl_com->cr, BIT(31));  in mctl_com_init()
435 		clrbits_le32(&mctl_com->cr, BIT(27));  in mctl_com_init()
437 		setbits_le32(&mctl_com->cr, BIT(27));  in mctl_com_init()
439 	if (para->clk > 408)  in mctl_com_init()
441 	else if (para->clk > 246)  in mctl_com_init()
445 	clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);  in mctl_com_init()
447 	/* TODO: half DQ, non-LPDDR3 types */  in mctl_com_init()
449 	       MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks) |  in mctl_com_init()
450 	       0x80000000, &mctl_ctl->mstr);  in mctl_com_init()
451 	writel(DCR_LPDDR3 | DCR_DDR8BANK | 0x400, &mctl_phy->dcr);  in mctl_com_init()
453 	if (para->ranks == 2)  in mctl_com_init()
454 		writel(0x0303, &mctl_ctl->odtmap);  in mctl_com_init()
456 		writel(0x0201, &mctl_ctl->odtmap);  in mctl_com_init()
458 	/* TODO: non-LPDDR3 types */  in mctl_com_init()
459 	tmp = para->clk * 7 / 2000;  in mctl_com_init()
462 	reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;  in mctl_com_init()
463 	writel(reg_val, &mctl_ctl->odtcfg);  in mctl_com_init()
476 		val = readl(&mctl_phy->dx[i].bdlr0);  in mctl_bit_delay_set()
478 			val += para->dx_write_delays[i][j] << (j * 8);  in mctl_bit_delay_set()
479 		writel(val, &mctl_phy->dx[i].bdlr0);  in mctl_bit_delay_set()
481 		val = readl(&mctl_phy->dx[i].bdlr1);  in mctl_bit_delay_set()
483 			val += para->dx_write_delays[i][j + 4] << (j * 8);  in mctl_bit_delay_set()
484 		writel(val, &mctl_phy->dx[i].bdlr1);  in mctl_bit_delay_set()
486 		val = readl(&mctl_phy->dx[i].bdlr2);  in mctl_bit_delay_set()
488 			val += para->dx_write_delays[i][j + 8] << (j * 8);  in mctl_bit_delay_set()
489 		writel(val, &mctl_phy->dx[i].bdlr2);  in mctl_bit_delay_set()
491 	clrbits_le32(&mctl_phy->pgcr[0], BIT(26));  in mctl_bit_delay_set()
494 		val = readl(&mctl_phy->dx[i].bdlr3);  in mctl_bit_delay_set()
496 			val += para->dx_read_delays[i][j] << (j * 8);  in mctl_bit_delay_set()
497 		writel(val, &mctl_phy->dx[i].bdlr3);  in mctl_bit_delay_set()
499 		val = readl(&mctl_phy->dx[i].bdlr4);  in mctl_bit_delay_set()
501 			val += para->dx_read_delays[i][j + 4] << (j * 8);  in mctl_bit_delay_set()
502 		writel(val, &mctl_phy->dx[i].bdlr4);  in mctl_bit_delay_set()
504 		val = readl(&mctl_phy->dx[i].bdlr5);  in mctl_bit_delay_set()
506 			val += para->dx_read_delays[i][j + 8] << (j * 8);  in mctl_bit_delay_set()
507 		writel(val, &mctl_phy->dx[i].bdlr5);  in mctl_bit_delay_set()
509 		val = readl(&mctl_phy->dx[i].bdlr6);  in mctl_bit_delay_set()
510 		val += (para->dx_read_delays[i][12] << 8) |  in mctl_bit_delay_set()
511 		       (para->dx_read_delays[i][13] << 16);  in mctl_bit_delay_set()
512 		writel(val, &mctl_phy->dx[i].bdlr6);  in mctl_bit_delay_set()
514 	setbits_le32(&mctl_phy->pgcr[0], BIT(26));  in mctl_bit_delay_set()
518 		val = readl(&mctl_phy->acbdlr[i]);  in mctl_bit_delay_set()
520 		writel(val, &mctl_phy->acbdlr[i]);  in mctl_bit_delay_set()
535 	setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));  in mctl_channel_init()
536 	setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));  in mctl_channel_init()
537 	writel(0x2f05, &mctl_ctl->sched[0]);  in mctl_channel_init()
538 	setbits_le32(&mctl_ctl->rfshctl3, BIT(0));  in mctl_channel_init()
539 	setbits_le32(&mctl_ctl->dfimisc, BIT(0));  in mctl_channel_init()
540 	setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));  in mctl_channel_init()
541 	clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);  in mctl_channel_init()
542 	/* TODO: non-LPDDR3 types */  in mctl_channel_init()
543 	clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));  in mctl_channel_init()
544 	clrbits_le32(&mctl_phy->pgcr[6], BIT(0));  in mctl_channel_init()
545 	clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);  in mctl_channel_init()
547 	clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);  in mctl_channel_init()
548 	clrbits_le32(&mctl_phy->vtcr[1], BIT(1));  in mctl_channel_init()
551 		clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);  in mctl_channel_init()
553 		clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);  in mctl_channel_init()
555 		clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);  in mctl_channel_init()
559 	if (para->ranks == 2)  in mctl_channel_init()
560 		setbits_le32(&mctl_phy->dtcr[1], 0x30000);  in mctl_channel_init()
562 		clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);  in mctl_channel_init()
564 	clrbits_le32(&mctl_phy->dtcr[1], BIT(1));  in mctl_channel_init()
565 	if (para->ranks == 2) {  in mctl_channel_init()
566 		writel(0x00010001, &mctl_phy->rankidr);  in mctl_channel_init()
567 		writel(0x20000, &mctl_phy->odtcr);  in mctl_channel_init()
569 		writel(0x0, &mctl_phy->rankidr);  in mctl_channel_init()
570 		writel(0x10000, &mctl_phy->odtcr);  in mctl_channel_init()
573 	/* TODO: non-LPDDR3 types */  in mctl_channel_init()
574 	clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);  in mctl_channel_init()
575 	if (para->clk <= 792) {  in mctl_channel_init()
576 		if (para->clk <= 672) {  in mctl_channel_init()
577 			if (para->clk <= 600)  in mctl_channel_init()
588 	clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);  in mctl_channel_init()
589 	clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,  in mctl_channel_init()
591 	clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);  in mctl_channel_init()
592 	setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);  in mctl_channel_init()
593 	setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);  in mctl_channel_init()
594 	setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);  in mctl_channel_init()
595 	clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);  in mctl_channel_init()
596 	setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);  in mctl_channel_init()
597 	setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);  in mctl_channel_init()
598 	setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);  in mctl_channel_init()
599 	if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {  in mctl_channel_init()
601 			writel(0x06060606, &mctl_phy->acbdlr[i]);  in mctl_channel_init()
604 	/* TODO: non-LPDDR3 types */  in mctl_channel_init()
609 	/* TODO: non-LPDDR3 types */  in mctl_channel_init()
611 		writel(0x00000909, &mctl_phy->dx[i].gcr[5]);  in mctl_channel_init()
618 		clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);  in mctl_channel_init()
624 		clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);  in mctl_channel_init()
630 	setbits_le32(&mctl_phy->pgcr[6], BIT(0));  in mctl_channel_init()
631 	clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);  in mctl_channel_init()
633 		clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);  in mctl_channel_init()
636 	if (readl(&mctl_phy->pgsr[0]) & 0x400000)  in mctl_channel_init()
642 		if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&  in mctl_channel_init()
643 		    (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 &&  in mctl_channel_init()
644 		    (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 &&  in mctl_channel_init()
645 		    (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) {  in mctl_channel_init()
646 			para->ranks = 1;  in mctl_channel_init()
656 	if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {  in mctl_channel_init()
659 		debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));  in mctl_channel_init()
661 			debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));  in mctl_channel_init()
665 	clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);  in mctl_channel_init()
666 	clrbits_le32(&mctl_phy->pgcr[1], 0x40);  in mctl_channel_init()
667 	clrbits_le32(&mctl_ctl->dfimisc, BIT(0));  in mctl_channel_init()
668 	writel(1, &mctl_ctl->swctl);  in mctl_channel_init()
669 	mctl_await_completion(&mctl_ctl->swstat, 1, 1);  in mctl_channel_init()
670 	clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));  in mctl_channel_init()
672 	setbits_le32(&mctl_com->unk_0x014, BIT(31));  in mctl_channel_init()
673 	writel(0xffffffff, &mctl_com->maer0);  in mctl_channel_init()
674 	writel(0x7ff, &mctl_com->maer1);  in mctl_channel_init()
675 	writel(0xffff, &mctl_com->maer2);  in mctl_channel_init()
680 	/* TODO: non-LPDDR3, half DQ */  in mctl_auto_detect_dram_size()
688 	para->cols = 8;  in mctl_auto_detect_dram_size()
689 	para->rows = 18;  in mctl_auto_detect_dram_size()
692 	for (para->rows = 13; para->rows < 18; para->rows++) {  in mctl_auto_detect_dram_size()
694 		if (mctl_mem_matches((1 << (para->rows + para->cols + 5))))  in mctl_auto_detect_dram_size()
699 	para->cols = 11;  in mctl_auto_detect_dram_size()
702 	for (para->cols = 8; para->cols < 11; para->cols++) {  in mctl_auto_detect_dram_size()
704 		if (mctl_mem_matches(1 << (para->cols + 2)))  in mctl_auto_detect_dram_size()
711 	/* TODO: non-LPDDR3, half DQ */  in mctl_calc_size()
713 	/* 8 banks, 32-bit (4 byte) data width */  in mctl_calc_size()
714 	return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;  in mctl_calc_size()
744 	/* RES_CAL_CTRL_REG in BSP U-boot*/  in sunxi_dram_init()
754 	clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);  in sunxi_dram_init()