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/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsi_dma.c32 * si_dma_is_lockup - Check if the DMA engine is locked up
43 u32 mask; in si_dma_is_lockup() local
45 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in si_dma_is_lockup()
46 mask = RADEON_RESET_DMA; in si_dma_is_lockup()
48 mask = RADEON_RESET_DMA1; in si_dma_is_lockup()
50 if (!(reset_mask & mask)) { in si_dma_is_lockup()
58 * si_dma_vm_copy_pages - update PTEs by copying them from the GART
64 * @count: number of page entries to update
66 * Update PTEs by copying them from the GART using the DMA (SI).
78 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, in si_dma_vm_copy_pages()
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H A Dcik_sdma.c38 * sDMA - System DMA
55 * cik_sdma_get_rptr - get the current read pointer
67 if (rdev->wb.enabled) { in cik_sdma_get_rptr()
68 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_sdma_get_rptr()
70 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_rptr()
82 * cik_sdma_get_wptr - get the current write pointer
94 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_get_wptr()
103 * cik_sdma_set_wptr - commit the write pointer
115 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cik_sdma_set_wptr()
120 WREG32(reg, (ring->wptr << 2) & 0x3fffc); in cik_sdma_set_wptr()
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/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dmicrochip,corepwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
37 microchip,sync-update-mask:
48 Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
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/openbmc/linux/include/sound/
H A Dhda_regmap.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * HD-audio regmap helpers
26 unsigned int mask, unsigned int val);
28 unsigned int mask, unsigned int val);
32 * snd_hdac_regmap_encode_verb - encode the verb to a pseudo register
42 * snd_hdac_regmap_encode_amp - encode the AMP verb to a pseudo register
57 * snd_hdac_regmap_encode_amp_stereo - encode a pseudo register for stereo AMPs
71 * snd_hdac_regmap_write - Write a verb with caching
88 * snd_hda_regmap_update - Update a verb value with caching
90 * @verb: verb to update
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/openbmc/linux/sound/soc/
H A Dsoc-jack.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-jack.c -- ALSA SoC jack handling
21 * snd_soc_jack_report - Report the current status for a jack
25 * @mask: a bitmask of enum snd_jack_type values that being reported.
34 void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask) in snd_soc_jack_report() argument
38 unsigned int sync = 0; in snd_soc_jack_report() local
40 if (!jack || !jack->jack) in snd_soc_jack_report()
42 trace_snd_soc_jack_report(jack, mask, status); in snd_soc_jack_report()
44 dapm = &jack->card->dapm; in snd_soc_jack_report()
46 mutex_lock(&jack->mutex); in snd_soc_jack_report()
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/openbmc/linux/arch/arm64/include/asm/vdso/
H A Dvsyscall.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * Update the vDSO data page to keep in sync with kernel timekeeping.
27 vdata[CS_HRES_COARSE].mask = VDSO_PRECISION_MASK; in __arm64_update_vsyscall()
28 vdata[CS_RAW].mask = VDSO_PRECISION_MASK; in __arm64_update_vsyscall()
32 /* The asm-generic header needs to be included after the definitions above */
33 #include <asm-generic/vdso/vsyscall.h>
/openbmc/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_netdev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
10 * fm10k_setup_tx_resources - allocate Tx resources (Descriptors)
17 struct device *dev = tx_ring->dev; in fm10k_setup_tx_resources()
20 size = sizeof(struct fm10k_tx_buffer) * tx_ring->count; in fm10k_setup_tx_resources()
22 tx_ring->tx_buffer = vzalloc(size); in fm10k_setup_tx_resources()
23 if (!tx_ring->tx_buffer) in fm10k_setup_tx_resources()
26 u64_stats_init(&tx_ring->syncp); in fm10k_setup_tx_resources()
29 tx_ring->size = tx_ring->count * sizeof(struct fm10k_tx_desc); in fm10k_setup_tx_resources()
30 tx_ring->size = ALIGN(tx_ring->size, 4096); in fm10k_setup_tx_resources()
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_ptp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #define PTP_SSIR 0x04 /* Sub-Second Increment Reg */
23 #define PTP_STSUR 0x10 /* System Time – Seconds Update Reg */
24 #define PTP_STNSUR 0x14 /* System Time – Nanoseconds Update Reg */
27 #define PTP_ATNR 0x48 /* Auxiliary Timestamp - Nanoseconds Reg */
28 #define PTP_ATSR 0x4c /* Auxiliary Timestamp - Seconds Reg */
37 #define PTP_DIGITAL_ROLLOVER_MODE 0x3B9ACA00 /* 10e9-1 ns */
42 #define PTP_TCR_TSCFUPDT BIT(1) /* Timestamp Fine/Coarse Update */
44 #define PTP_TCR_TSUPDT BIT(3) /* Timestamp Update */
46 #define PTP_TCR_TSADDREG BIT(5) /* Addend Reg Update */
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/openbmc/linux/sound/hda/
H A Dhdac_regmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Regmap support for HD-audio verbs
9 * - Provided for not all verbs but only subset standard non-volatile verbs.
10 * - For reading, only AC_VERB_GET_* variants can be used.
11 * - For writing, mapped to the *corresponding* AC_VERB_SET_* variants,
45 return !codec->cache_coef; in hda_volatile_reg()
58 case AC_VERB_GET_DEVICE_LIST: /* read-only volatile */ in hda_volatile_reg()
72 snd_array_for_each(&codec->vendor_verbs, i, v) { in hda_writeable_reg()
77 if (codec->caps_overwriting) in hda_writeable_reg()
85 return codec->cache_coef; in hda_writeable_reg()
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/openbmc/linux/sound/soc/stm/
H A Dstm32_sai_sub.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
10 #include <linux/clk-provider.h>
41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK)
42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE)
47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif)
54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm)
55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm)
56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4(sai->pdata))
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/openbmc/linux/drivers/gpio/
H A Dgpio-crystalcove.c1 // SPDX-License-Identifier: GPL-2.0
65 * struct crystalcove_gpio - Crystal Cove GPIO controller
66 * @buslock: for bus lock/sync and unlock.
69 * @update: pending IRQ setting update, to be written to the chip upon unlock.
71 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
77 int update; member
95 return -ENOTSUPP; in to_reg()
117 int mask = BIT(gpio % 8); in crystalcove_update_irq_mask() local
119 if (cg->set_irq_mask) in crystalcove_update_irq_mask()
120 regmap_update_bits(cg->regmap, mirqs0, mask, mask); in crystalcove_update_irq_mask()
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H A Dgpio-wcove.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver is written based on gpio-crystalcove.c
21 * Bank 0: Pin 0 - 6
22 * Bank 1: Pin 7 - 10
23 * Bank 2: Pin 11 - 12
31 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
33 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
38 * Group 0: Bank 0 pins (Pin 0 - 6)
39 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
40 * Each group has two registers (one bit per pin): status and mask.
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/openbmc/linux/include/linux/
H A Dptp_classify.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define PTP_CLASS_PMASK 0x70 /* mask for the packet type field */
57 #define IPV4_HLEN(data) (((struct iphdr *)(data + OFF_IHL))->ihl << 2)
85 * ptp_classify_raw - classify a PTP packet
97 * ptp_parse_header - Get pointer to the PTP v2 header
112 * ptp_get_msgtype - Extract ptp message type from given header
128 msgtype = hdr->control; in ptp_get_msgtype()
130 msgtype = hdr->tsmt & 0x0f; in ptp_get_msgtype()
137 * ptp_check_diff8 - Computes new checksum (when altering a 64-bit field)
155 * ptp_header_update_correction - Update PTP header's correction field
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/openbmc/linux/sound/pci/pcxhr/
H A Dpcxhr_mixer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #define PCXHR_LINE_CAPTURE_LEVEL_MIN 0 /* -112.0 dB */
27 #define PCXHR_LINE_CAPTURE_ZERO_LEVEL 224 /* 0.0 dB ( 0 dBu -> 0 dBFS ) */
29 #define PCXHR_LINE_PLAYBACK_LEVEL_MIN 0 /* -104.0 dB */
31 #define PCXHR_LINE_PLAYBACK_ZERO_LEVEL 104 /* 0.0 dB ( 0 dBFS -> 0 dBu ) */
33 static const DECLARE_TLV_DB_SCALE(db_scale_analog_capture, -11200, 50, 1550);
34 static const DECLARE_TLV_DB_SCALE(db_scale_analog_playback, -10400, 100, 2400);
36 static const DECLARE_TLV_DB_SCALE(db_scale_a_hr222_capture, -11150, 50, 1600);
37 static const DECLARE_TLV_DB_SCALE(db_scale_a_hr222_playback, -2550, 50, 2400);
48 rmh.cmd[2] = chip->analog_capture_volume[channel]; in pcxhr_update_analog_audio_level()
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/openbmc/linux/include/linux/firmware/intel/
H A Dstratix10-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
9 #include <linux/arm-smccc.h>
19 * An ARM SMC instruction takes a function identifier and up to 6 64-bit
20 * register values as arguments, and can return up to 4 64-bit register
31 * STD call starts a operation which can be preempted by a non-secure
69 * There is error during the process of remote status update request.
81 * Sync call used by service driver at EL1 to request the FPGA in EL3 to
88 * a2-7: not used.
92 * a1-3: not used.
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/openbmc/linux/include/uapi/linux/
H A Dip_vs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
23 #define IP_VS_SVC_F_ONEPACKET 0x0004 /* one-packet scheduling */
38 * IPVS sync daemon states
82 #define IP_VS_CONN_F_FWD_MASK 0x0007 /* mask for the fwd methods */
88 #define IP_VS_CONN_F_SYNC 0x0020 /* entry created by sync */
94 #define IP_VS_CONN_F_SEQ_MASK 0x0600 /* in/out sequence mask */
108 /* Bits allowed to update in backup server */
281 /* sync daemon state (master/backup) */
304 __u32 mask; member
321 IPVS_CMD_NEW_DAEMON, /* start sync daemon */
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/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-icicle-kit-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
9 compatible = "microchip,corepwm-rtl-v4";
11 microchip,sync-update-mask = /bits/ 32 <0>;
12 #pwm-cells = <3>;
18 compatible = "microchip,corei2c-rtl-v7";
20 #address-cells = <1>;
21 #size-cells = <0>;
23 interrupt-parent = <&plic>;
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/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Ddisp.c31 #include <linux/dma-mapping.h>
83 chan->device = device; in nv50_chan_create()
94 &chan->user); in nv50_chan_create()
96 nvif_object_map(&chan->user, NULL, 0); in nv50_chan_create()
105 return -ENOSYS; in nv50_chan_create()
111 nvif_object_dtor(&chan->user); in nv50_chan_destroy()
121 nvif_object_dtor(&dmac->vram); in nv50_dmac_destroy()
122 nvif_object_dtor(&dmac->sync); in nv50_dmac_destroy()
124 nv50_chan_destroy(&dmac->base); in nv50_dmac_destroy()
126 nvif_mem_dtor(&dmac->_push.mem); in nv50_dmac_destroy()
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/openbmc/linux/arch/arm/mach-omap2/
H A Dsram243x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram243x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
50 mvn r9, #0x4 @ mask to get clear bit2
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
94 * wait for it to finish, use 32k sync counter, 1tick=31uS.
[all …]
H A Dsram242x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram242x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
50 mvn r9, #0x4 @ mask to get clear bit2
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
94 * wait for it to finish, use 32k sync counter, 1tick=31uS.
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/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dsubcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
37 * ------------|------------------
39 * 2-way split | 2
40 * 4-way split | 4
46 * ----------------------------
48 * ----------------------------
50 * ----------------------------
52 * 2-way split:
53 * -------------------------------------
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/openbmc/linux/arch/riscv/kvm/
H A Dvcpu.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/entry-kvm.h>
47 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_reset_vcpu()
48 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; in kvm_riscv_reset_vcpu()
49 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_reset_vcpu()
50 struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context; in kvm_riscv_reset_vcpu()
59 loaded = (vcpu->cpu != -1); in kvm_riscv_reset_vcpu()
63 vcpu->arch.last_exit_cpu = -1; in kvm_riscv_reset_vcpu()
77 bitmap_zero(vcpu->arch.irqs_pending, KVM_RISCV_VCPU_NR_IRQS); in kvm_riscv_reset_vcpu()
78 bitmap_zero(vcpu->arch.irqs_pending_mask, KVM_RISCV_VCPU_NR_IRQS); in kvm_riscv_reset_vcpu()
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/openbmc/linux/arch/x86/kernel/
H A Dtsc_sync.c1 // SPDX-License-Identifier: GPL-2.0
8 * print a warning if not and turn off the TSC clock-source.
10 * The warp-check is point-to-point between two CPUs, the CPU
14 * Only two CPUs may participate - they can enter in any order.
63 if (!resume && time_before(jiffies, adj->nextcheck)) in tsc_verify_tsc_adjust()
66 adj->nextcheck = jiffies + HZ; in tsc_verify_tsc_adjust()
69 if (adj->adjusted == curval) in tsc_verify_tsc_adjust()
73 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); in tsc_verify_tsc_adjust()
75 if (!adj->warned || resume) { in tsc_verify_tsc_adjust()
76 pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n", in tsc_verify_tsc_adjust()
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/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
88 /* Loop limit on how long we wait for auto-negotiation to complete */
170 /* 1000BASE-T Control Register */
174 /* 1000BASE-T Status Register */
194 #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */
195 #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done*/
224 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
238 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
262 #define IGC_ICR_TS BIT(19) /* Time Sync Interrupt */
277 /* Interrupt Mask Set */
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/openbmc/linux/sound/soc/tegra/
H A Dtegra210_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_i2s.c - Tegra210 I2S driver
29 * Below update does not have any effect on Tegra186 and Tegra194.
30 * On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update
42 regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1); in tegra210_i2s_set_slot_ctrl()
54 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val); in tegra210_i2s_set_clock_rate()
60 err = clk_set_rate(i2s->clk_i2s, clock_rate); in tegra210_i2s_set_clock_rate()
67 if (!IS_ERR(i2s->clk_sync_input)) { in tegra210_i2s_set_clock_rate()
70 * clock. Below sets sync input clock rate as per bclk, in tegra210_i2s_set_clock_rate()
73 err = clk_set_rate(i2s->clk_sync_input, clock_rate); in tegra210_i2s_set_clock_rate()
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