14fa9c49fSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2891434b1SRayagond Kokatanur /******************************************************************************
3891434b1SRayagond Kokatanur   PTP Header file
4891434b1SRayagond Kokatanur 
5891434b1SRayagond Kokatanur   Copyright (C) 2013  Vayavya Labs Pvt Ltd
6891434b1SRayagond Kokatanur 
7891434b1SRayagond Kokatanur 
8891434b1SRayagond Kokatanur   Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
9891434b1SRayagond Kokatanur ******************************************************************************/
10891434b1SRayagond Kokatanur 
11891434b1SRayagond Kokatanur #ifndef	__STMMAC_PTP_H__
12891434b1SRayagond Kokatanur #define	__STMMAC_PTP_H__
13891434b1SRayagond Kokatanur 
144bb7aff9SJose Abreu #define PTP_XGMAC_OFFSET	0xd00
15d2042052SGiuseppe CAVALLARO #define	PTP_GMAC4_OFFSET	0xb00
16d2042052SGiuseppe CAVALLARO #define	PTP_GMAC3_X_OFFSET	0x700
17d2042052SGiuseppe CAVALLARO 
18891434b1SRayagond Kokatanur /* IEEE 1588 PTP register offsets */
19d2042052SGiuseppe CAVALLARO #define	PTP_TCR		0x00	/* Timestamp Control Reg */
20d2042052SGiuseppe CAVALLARO #define	PTP_SSIR	0x04	/* Sub-Second Increment Reg */
21d2042052SGiuseppe CAVALLARO #define	PTP_STSR	0x08	/* System Time – Seconds Regr */
22d2042052SGiuseppe CAVALLARO #define	PTP_STNSR	0x0c	/* System Time – Nanoseconds Reg */
23d2042052SGiuseppe CAVALLARO #define	PTP_STSUR	0x10	/* System Time – Seconds Update Reg */
24d2042052SGiuseppe CAVALLARO #define	PTP_STNSUR	0x14	/* System Time – Nanoseconds Update Reg */
25d2042052SGiuseppe CAVALLARO #define	PTP_TAR		0x18	/* Timestamp Addend Reg */
26341f67e4STan Tee Min #define	PTP_ACR		0x40	/* Auxiliary Control Reg */
27341f67e4STan Tee Min #define	PTP_ATNR	0x48	/* Auxiliary Timestamp - Nanoseconds Reg */
28341f67e4STan Tee Min #define	PTP_ATSR	0x4c	/* Auxiliary Timestamp - Seconds Reg */
29*26cfb838SJohannes Zink #define	PTP_TS_INGR_CORR_NS	0x58	/* Ingress timestamp correction nanoseconds */
30*26cfb838SJohannes Zink #define	PTP_TS_EGR_CORR_NS	0x5C	/* Egress timestamp correction nanoseconds*/
31*26cfb838SJohannes Zink #define	PTP_TS_INGR_CORR_SNS	0x60	/* Ingress timestamp correction subnanoseconds */
32*26cfb838SJohannes Zink #define	PTP_TS_EGR_CORR_SNS	0x64	/* Egress timestamp correction subnanoseconds */
33*26cfb838SJohannes Zink #define	PTP_TS_INGR_LAT	0x68	/* MAC internal Ingress Latency */
34*26cfb838SJohannes Zink #define	PTP_TS_EGR_LAT	0x6c	/* MAC internal Egress Latency */
35891434b1SRayagond Kokatanur 
36891434b1SRayagond Kokatanur #define	PTP_STNSUR_ADDSUB_SHIFT	31
37d2042052SGiuseppe CAVALLARO #define	PTP_DIGITAL_ROLLOVER_MODE	0x3B9ACA00	/* 10e9-1 ns */
38d2042052SGiuseppe CAVALLARO #define	PTP_BINARY_ROLLOVER_MODE	0x80000000	/* ~0.466 ns */
39891434b1SRayagond Kokatanur 
40d2042052SGiuseppe CAVALLARO /* PTP Timestamp control register defines */
41d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSENA		BIT(0)	/* Timestamp Enable */
42d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSCFUPDT	BIT(1)	/* Timestamp Fine/Coarse Update */
43d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSINIT		BIT(2)	/* Timestamp Initialize */
44d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSUPDT		BIT(3)	/* Timestamp Update */
45d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSTRIG		BIT(4)	/* Timestamp Interrupt Trigger Enable */
46d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSADDREG	BIT(5)	/* Addend Reg Update */
47d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSENALL		BIT(8)	/* Enable Timestamp for All Frames */
48d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSCTRLSSR	BIT(9)	/* Digital or Binary Rollover Control */
49891434b1SRayagond Kokatanur /* Enable PTP packet Processing for Version 2 Format */
50d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSVER2ENA	BIT(10)
51891434b1SRayagond Kokatanur /* Enable Processing of PTP over Ethernet Frames */
52d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSIPENA		BIT(11)
53891434b1SRayagond Kokatanur /* Enable Processing of PTP Frames Sent over IPv6-UDP */
54d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSIPV6ENA	BIT(12)
55891434b1SRayagond Kokatanur /* Enable Processing of PTP Frames Sent over IPv4-UDP */
56d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSIPV4ENA	BIT(13)
57891434b1SRayagond Kokatanur /* Enable Timestamp Snapshot for Event Messages */
58d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSEVNTENA	BIT(14)
59891434b1SRayagond Kokatanur /* Enable Snapshot for Messages Relevant to Master */
60d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSMSTRENA	BIT(15)
617d8e249fSIlias Apalodimas /* Select PTP packets for Taking Snapshots
627d8e249fSIlias Apalodimas  * On gmac4 specifically:
637d8e249fSIlias Apalodimas  * Enable SYNC, Pdelay_Req, Pdelay_Resp when TSEVNTENA is enabled.
647d8e249fSIlias Apalodimas  * or
657d8e249fSIlias Apalodimas  * Enable  SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp,
667d8e249fSIlias Apalodimas  * Pdelay_Resp_Follow_Up if TSEVNTENA is disabled
677d8e249fSIlias Apalodimas  */
68fd6720aeSMario Molitor #define	PTP_TCR_SNAPTYPSEL_1	BIT(16)
69891434b1SRayagond Kokatanur /* Enable MAC address for PTP Frame Filtering */
70d2042052SGiuseppe CAVALLARO #define	PTP_TCR_TSENMACADDR	BIT(18)
71d2042052SGiuseppe CAVALLARO 
72d2042052SGiuseppe CAVALLARO /* SSIR defines */
73ede5a389SPiergiorgio Beruto #define	PTP_SSIR_SSINC_MAX		0xff
74d2042052SGiuseppe CAVALLARO #define	GMAC4_PTP_SSIR_SSINC_SHIFT	16
75891434b1SRayagond Kokatanur 
76341f67e4STan Tee Min /* Auxiliary Control defines */
77341f67e4STan Tee Min #define	PTP_ACR_ATSFC		BIT(0)	/* Auxiliary Snapshot FIFO Clear */
78341f67e4STan Tee Min #define	PTP_ACR_ATSEN0		BIT(4)	/* Auxiliary Snapshot 0 Enable */
79341f67e4STan Tee Min #define	PTP_ACR_ATSEN1		BIT(5)	/* Auxiliary Snapshot 1 Enable */
80341f67e4STan Tee Min #define	PTP_ACR_ATSEN2		BIT(6)	/* Auxiliary Snapshot 2 Enable */
81341f67e4STan Tee Min #define	PTP_ACR_ATSEN3		BIT(7)	/* Auxiliary Snapshot 3 Enable */
82f4da5652STan Tee Min #define	PTP_ACR_ATSEN_SHIFT	5	/* Auxiliary Snapshot shift */
83341f67e4STan Tee Min #define	PTP_ACR_MASK		GENMASK(7, 4)	/* Aux Snapshot Mask */
84341f67e4STan Tee Min #define	PMC_ART_VALUE0		0x01	/* PMC_ART[15:0] timer value */
85341f67e4STan Tee Min #define	PMC_ART_VALUE1		0x02	/* PMC_ART[31:16] timer value */
86341f67e4STan Tee Min #define	PMC_ART_VALUE2		0x03	/* PMC_ART[47:32] timer value */
87341f67e4STan Tee Min #define	PMC_ART_VALUE3		0x04	/* PMC_ART[63:48] timer value */
88341f67e4STan Tee Min #define	GMAC4_ART_TIME_SHIFT	16	/* ART TIME 16-bits shift */
89341f67e4STan Tee Min 
90341f67e4STan Tee Min enum aux_snapshot {
91341f67e4STan Tee Min 	AUX_SNAPSHOT0 = 0x10,
92341f67e4STan Tee Min 	AUX_SNAPSHOT1 = 0x20,
93341f67e4STan Tee Min 	AUX_SNAPSHOT2 = 0x40,
94341f67e4STan Tee Min 	AUX_SNAPSHOT3 = 0x80,
95341f67e4STan Tee Min };
96341f67e4STan Tee Min 
97891434b1SRayagond Kokatanur #endif	/* __STMMAC_PTP_H__ */
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