12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2e2186023SMichael Ellerman /*
3e2186023SMichael Ellerman * Copyright 2013, Michael (Ellerman|Neuling), IBM Corporation.
4e2186023SMichael Ellerman */
5e2186023SMichael Ellerman
6e2186023SMichael Ellerman #define pr_fmt(fmt) "powernv: " fmt
7e2186023SMichael Ellerman
8e2186023SMichael Ellerman #include <linux/kernel.h>
9e2186023SMichael Ellerman #include <linux/cpu.h>
10e2186023SMichael Ellerman #include <linux/cpumask.h>
11e2186023SMichael Ellerman #include <linux/device.h>
12e2186023SMichael Ellerman #include <linux/gfp.h>
13e2186023SMichael Ellerman #include <linux/smp.h>
14e2186023SMichael Ellerman #include <linux/stop_machine.h>
15e2186023SMichael Ellerman
16e2186023SMichael Ellerman #include <asm/cputhreads.h>
172201f994SNicholas Piggin #include <asm/cpuidle.h>
18e2186023SMichael Ellerman #include <asm/kvm_ppc.h>
19e2186023SMichael Ellerman #include <asm/machdep.h>
20e2186023SMichael Ellerman #include <asm/opal.h>
21e2186023SMichael Ellerman #include <asm/smp.h>
22e2186023SMichael Ellerman
23*4c8c3c7fSValentin Schneider #include <trace/events/ipi.h>
24*4c8c3c7fSValentin Schneider
25e2186023SMichael Ellerman #include "subcore.h"
261217d34bSAnton Blanchard #include "powernv.h"
27e2186023SMichael Ellerman
28e2186023SMichael Ellerman
29e2186023SMichael Ellerman /*
30e2186023SMichael Ellerman * Split/unsplit procedure:
31e2186023SMichael Ellerman *
32e2186023SMichael Ellerman * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
33e2186023SMichael Ellerman *
34e2186023SMichael Ellerman * The mapping to subcores_per_core is simple:
35e2186023SMichael Ellerman *
36e2186023SMichael Ellerman * State | subcores_per_core
37e2186023SMichael Ellerman * ------------|------------------
38e2186023SMichael Ellerman * Unsplit | 1
39e2186023SMichael Ellerman * 2-way split | 2
40e2186023SMichael Ellerman * 4-way split | 4
41e2186023SMichael Ellerman *
42e2186023SMichael Ellerman * The core is split along thread boundaries, the mapping between subcores and
43e2186023SMichael Ellerman * threads is as follows:
44e2186023SMichael Ellerman *
45e2186023SMichael Ellerman * Unsplit:
46e2186023SMichael Ellerman * ----------------------------
47e2186023SMichael Ellerman * Subcore | 0 |
48e2186023SMichael Ellerman * ----------------------------
49e2186023SMichael Ellerman * Thread | 0 1 2 3 4 5 6 7 |
50e2186023SMichael Ellerman * ----------------------------
51e2186023SMichael Ellerman *
52e2186023SMichael Ellerman * 2-way split:
53e2186023SMichael Ellerman * -------------------------------------
54e2186023SMichael Ellerman * Subcore | 0 | 1 |
55e2186023SMichael Ellerman * -------------------------------------
56e2186023SMichael Ellerman * Thread | 0 1 2 3 | 4 5 6 7 |
57e2186023SMichael Ellerman * -------------------------------------
58e2186023SMichael Ellerman *
59e2186023SMichael Ellerman * 4-way split:
60e2186023SMichael Ellerman * -----------------------------------------
61e2186023SMichael Ellerman * Subcore | 0 | 1 | 2 | 3 |
62e2186023SMichael Ellerman * -----------------------------------------
63e2186023SMichael Ellerman * Thread | 0 1 | 2 3 | 4 5 | 6 7 |
64e2186023SMichael Ellerman * -----------------------------------------
65e2186023SMichael Ellerman *
66e2186023SMichael Ellerman *
67e2186023SMichael Ellerman * Transitions
68e2186023SMichael Ellerman * -----------
69e2186023SMichael Ellerman *
70e2186023SMichael Ellerman * It is not possible to transition between either of the split states, the
71e2186023SMichael Ellerman * core must first be unsplit. The legal transitions are:
72e2186023SMichael Ellerman *
73e2186023SMichael Ellerman * ----------- ---------------
74e2186023SMichael Ellerman * | | <----> | 2-way split |
75e2186023SMichael Ellerman * | | ---------------
76e2186023SMichael Ellerman * | Unsplit |
77e2186023SMichael Ellerman * | | ---------------
78e2186023SMichael Ellerman * | | <----> | 4-way split |
79e2186023SMichael Ellerman * ----------- ---------------
80e2186023SMichael Ellerman *
81e2186023SMichael Ellerman * Unsplitting
82e2186023SMichael Ellerman * -----------
83e2186023SMichael Ellerman *
84e2186023SMichael Ellerman * Unsplitting is the simpler procedure. It requires thread 0 to request the
85e2186023SMichael Ellerman * unsplit while all other threads NAP.
86e2186023SMichael Ellerman *
87e2186023SMichael Ellerman * Thread 0 clears HID0_POWER8_DYNLPARDIS (Dynamic LPAR Disable). This tells
88e2186023SMichael Ellerman * the hardware that if all threads except 0 are napping, the hardware should
89e2186023SMichael Ellerman * unsplit the core.
90e2186023SMichael Ellerman *
91e2186023SMichael Ellerman * Non-zero threads are sent to a NAP loop, they don't exit the loop until they
92e2186023SMichael Ellerman * see the core unsplit.
93e2186023SMichael Ellerman *
94e2186023SMichael Ellerman * Core 0 spins waiting for the hardware to see all the other threads napping
95e2186023SMichael Ellerman * and perform the unsplit.
96e2186023SMichael Ellerman *
97e2186023SMichael Ellerman * Once thread 0 sees the unsplit, it IPIs the secondary threads to wake them
98e2186023SMichael Ellerman * out of NAP. They will then see the core unsplit and exit the NAP loop.
99e2186023SMichael Ellerman *
100e2186023SMichael Ellerman * Splitting
101e2186023SMichael Ellerman * ---------
102e2186023SMichael Ellerman *
103e2186023SMichael Ellerman * The basic splitting procedure is fairly straight forward. However it is
104e2186023SMichael Ellerman * complicated by the fact that after the split occurs, the newly created
105e2186023SMichael Ellerman * subcores are not in a fully initialised state.
106e2186023SMichael Ellerman *
107e2186023SMichael Ellerman * Most notably the subcores do not have the correct value for SDR1, which
108e2186023SMichael Ellerman * means they must not be running in virtual mode when the split occurs. The
109e2186023SMichael Ellerman * subcores have separate timebases SPRs but these are pre-synchronised by
110e2186023SMichael Ellerman * opal.
111e2186023SMichael Ellerman *
112e2186023SMichael Ellerman * To begin with secondary threads are sent to an assembly routine. There they
113e2186023SMichael Ellerman * switch to real mode, so they are immune to the uninitialised SDR1 value.
114e2186023SMichael Ellerman * Once in real mode they indicate that they are in real mode, and spin waiting
115e2186023SMichael Ellerman * to see the core split.
116e2186023SMichael Ellerman *
117e2186023SMichael Ellerman * Thread 0 waits to see that all secondaries are in real mode, and then begins
118e2186023SMichael Ellerman * the splitting procedure. It firstly sets HID0_POWER8_DYNLPARDIS, which
119e2186023SMichael Ellerman * prevents the hardware from unsplitting. Then it sets the appropriate HID bit
120e2186023SMichael Ellerman * to request the split, and spins waiting to see that the split has happened.
121e2186023SMichael Ellerman *
122e2186023SMichael Ellerman * Concurrently the secondaries will notice the split. When they do they set up
123e2186023SMichael Ellerman * their SPRs, notably SDR1, and then they can return to virtual mode and exit
124e2186023SMichael Ellerman * the procedure.
125e2186023SMichael Ellerman */
126e2186023SMichael Ellerman
127e2186023SMichael Ellerman /* Initialised at boot by subcore_init() */
128e2186023SMichael Ellerman static int subcores_per_core;
129e2186023SMichael Ellerman
130e2186023SMichael Ellerman /*
131e2186023SMichael Ellerman * Used to communicate to offline cpus that we want them to pop out of the
132e2186023SMichael Ellerman * offline loop and do a split or unsplit.
133e2186023SMichael Ellerman *
134e2186023SMichael Ellerman * 0 - no split happening
135e2186023SMichael Ellerman * 1 - unsplit in progress
136e2186023SMichael Ellerman * 2 - split to 2 in progress
137e2186023SMichael Ellerman * 4 - split to 4 in progress
138e2186023SMichael Ellerman */
139e2186023SMichael Ellerman static int new_split_mode;
140e2186023SMichael Ellerman
141e2186023SMichael Ellerman static cpumask_var_t cpu_offline_mask;
142e2186023SMichael Ellerman
143e2186023SMichael Ellerman struct split_state {
144e2186023SMichael Ellerman u8 step;
145e2186023SMichael Ellerman u8 master;
146e2186023SMichael Ellerman };
147e2186023SMichael Ellerman
148e2186023SMichael Ellerman static DEFINE_PER_CPU(struct split_state, split_state);
149e2186023SMichael Ellerman
wait_for_sync_step(int step)150e2186023SMichael Ellerman static void wait_for_sync_step(int step)
151e2186023SMichael Ellerman {
152e2186023SMichael Ellerman int i, cpu = smp_processor_id();
153e2186023SMichael Ellerman
154e2186023SMichael Ellerman for (i = cpu + 1; i < cpu + threads_per_core; i++)
155e2186023SMichael Ellerman while(per_cpu(split_state, i).step < step)
156e2186023SMichael Ellerman barrier();
157e2186023SMichael Ellerman
158e2186023SMichael Ellerman /* Order the wait loop vs any subsequent loads/stores. */
159e2186023SMichael Ellerman mb();
160e2186023SMichael Ellerman }
161e2186023SMichael Ellerman
update_hid_in_slw(u64 hid0)16277b54e9fSShreyas B. Prabhu static void update_hid_in_slw(u64 hid0)
16377b54e9fSShreyas B. Prabhu {
16477b54e9fSShreyas B. Prabhu u64 idle_states = pnv_get_supported_cpuidle_states();
16577b54e9fSShreyas B. Prabhu
16677b54e9fSShreyas B. Prabhu if (idle_states & OPAL_PM_WINKLE_ENABLED) {
16777b54e9fSShreyas B. Prabhu /* OPAL call to patch slw with the new HID0 value */
16877b54e9fSShreyas B. Prabhu u64 cpu_pir = hard_smp_processor_id();
16977b54e9fSShreyas B. Prabhu
17077b54e9fSShreyas B. Prabhu opal_slw_set_reg(cpu_pir, SPRN_HID0, hid0);
17177b54e9fSShreyas B. Prabhu }
17277b54e9fSShreyas B. Prabhu }
17377b54e9fSShreyas B. Prabhu
update_power8_hid0(unsigned long hid0)174ab3aab29SChristophe Leroy static inline void update_power8_hid0(unsigned long hid0)
175ab3aab29SChristophe Leroy {
176ab3aab29SChristophe Leroy /*
177ab3aab29SChristophe Leroy * The HID0 update on Power8 should at the very least be
178ab3aab29SChristophe Leroy * preceded by a SYNC instruction followed by an ISYNC
179ab3aab29SChristophe Leroy * instruction
180ab3aab29SChristophe Leroy */
181ab3aab29SChristophe Leroy asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
182ab3aab29SChristophe Leroy }
183ab3aab29SChristophe Leroy
unsplit_core(void)184e2186023SMichael Ellerman static void unsplit_core(void)
185e2186023SMichael Ellerman {
186e2186023SMichael Ellerman u64 hid0, mask;
187e2186023SMichael Ellerman int i, cpu;
188e2186023SMichael Ellerman
189e2186023SMichael Ellerman mask = HID0_POWER8_2LPARMODE | HID0_POWER8_4LPARMODE;
190e2186023SMichael Ellerman
191e2186023SMichael Ellerman cpu = smp_processor_id();
192e2186023SMichael Ellerman if (cpu_thread_in_core(cpu) != 0) {
193e2186023SMichael Ellerman while (mfspr(SPRN_HID0) & mask)
19410d91611SNicholas Piggin power7_idle_type(PNV_THREAD_NAP);
195e2186023SMichael Ellerman
196e2186023SMichael Ellerman per_cpu(split_state, cpu).step = SYNC_STEP_UNSPLIT;
197e2186023SMichael Ellerman return;
198e2186023SMichael Ellerman }
199e2186023SMichael Ellerman
200e2186023SMichael Ellerman hid0 = mfspr(SPRN_HID0);
201e2186023SMichael Ellerman hid0 &= ~HID0_POWER8_DYNLPARDIS;
202e63dbd16SGautham R. Shenoy update_power8_hid0(hid0);
20377b54e9fSShreyas B. Prabhu update_hid_in_slw(hid0);
204e2186023SMichael Ellerman
205e2186023SMichael Ellerman while (mfspr(SPRN_HID0) & mask)
206e2186023SMichael Ellerman cpu_relax();
207e2186023SMichael Ellerman
208e2186023SMichael Ellerman /* Wake secondaries out of NAP */
209e2186023SMichael Ellerman for (i = cpu + 1; i < cpu + threads_per_core; i++)
210e2186023SMichael Ellerman smp_send_reschedule(i);
211e2186023SMichael Ellerman
212e2186023SMichael Ellerman wait_for_sync_step(SYNC_STEP_UNSPLIT);
213e2186023SMichael Ellerman }
214e2186023SMichael Ellerman
split_core(int new_mode)215e2186023SMichael Ellerman static void split_core(int new_mode)
216e2186023SMichael Ellerman {
217e2186023SMichael Ellerman struct { u64 value; u64 mask; } split_parms[2] = {
218e2186023SMichael Ellerman { HID0_POWER8_1TO2LPAR, HID0_POWER8_2LPARMODE },
219e2186023SMichael Ellerman { HID0_POWER8_1TO4LPAR, HID0_POWER8_4LPARMODE }
220e2186023SMichael Ellerman };
221e2186023SMichael Ellerman int i, cpu;
222e2186023SMichael Ellerman u64 hid0;
223e2186023SMichael Ellerman
224e2186023SMichael Ellerman /* Convert new_mode (2 or 4) into an index into our parms array */
225e2186023SMichael Ellerman i = (new_mode >> 1) - 1;
226e2186023SMichael Ellerman BUG_ON(i < 0 || i > 1);
227e2186023SMichael Ellerman
228e2186023SMichael Ellerman cpu = smp_processor_id();
229e2186023SMichael Ellerman if (cpu_thread_in_core(cpu) != 0) {
230e2186023SMichael Ellerman split_core_secondary_loop(&per_cpu(split_state, cpu).step);
231e2186023SMichael Ellerman return;
232e2186023SMichael Ellerman }
233e2186023SMichael Ellerman
234e2186023SMichael Ellerman wait_for_sync_step(SYNC_STEP_REAL_MODE);
235e2186023SMichael Ellerman
236e2186023SMichael Ellerman /* Write new mode */
237e2186023SMichael Ellerman hid0 = mfspr(SPRN_HID0);
238e2186023SMichael Ellerman hid0 |= HID0_POWER8_DYNLPARDIS | split_parms[i].value;
239e63dbd16SGautham R. Shenoy update_power8_hid0(hid0);
24077b54e9fSShreyas B. Prabhu update_hid_in_slw(hid0);
241e2186023SMichael Ellerman
242e2186023SMichael Ellerman /* Wait for it to happen */
243e2186023SMichael Ellerman while (!(mfspr(SPRN_HID0) & split_parms[i].mask))
244e2186023SMichael Ellerman cpu_relax();
245e2186023SMichael Ellerman }
246e2186023SMichael Ellerman
cpu_do_split(int new_mode)247e2186023SMichael Ellerman static void cpu_do_split(int new_mode)
248e2186023SMichael Ellerman {
249e2186023SMichael Ellerman /*
250e2186023SMichael Ellerman * At boot subcores_per_core will be 0, so we will always unsplit at
251e2186023SMichael Ellerman * boot. In the usual case where the core is already unsplit it's a
252e2186023SMichael Ellerman * nop, and this just ensures the kernel's notion of the mode is
253e2186023SMichael Ellerman * consistent with the hardware.
254e2186023SMichael Ellerman */
255e2186023SMichael Ellerman if (subcores_per_core != 1)
256e2186023SMichael Ellerman unsplit_core();
257e2186023SMichael Ellerman
258e2186023SMichael Ellerman if (new_mode != 1)
259e2186023SMichael Ellerman split_core(new_mode);
260e2186023SMichael Ellerman
261e2186023SMichael Ellerman mb();
262e2186023SMichael Ellerman per_cpu(split_state, smp_processor_id()).step = SYNC_STEP_FINISHED;
263e2186023SMichael Ellerman }
264e2186023SMichael Ellerman
cpu_core_split_required(void)265e2186023SMichael Ellerman bool cpu_core_split_required(void)
266e2186023SMichael Ellerman {
267e2186023SMichael Ellerman smp_rmb();
268e2186023SMichael Ellerman
269e2186023SMichael Ellerman if (!new_split_mode)
270e2186023SMichael Ellerman return false;
271e2186023SMichael Ellerman
272e2186023SMichael Ellerman cpu_do_split(new_split_mode);
273e2186023SMichael Ellerman
274e2186023SMichael Ellerman return true;
275e2186023SMichael Ellerman }
276e2186023SMichael Ellerman
update_subcore_sibling_mask(void)27777b54e9fSShreyas B. Prabhu void update_subcore_sibling_mask(void)
27877b54e9fSShreyas B. Prabhu {
27977b54e9fSShreyas B. Prabhu int cpu;
28077b54e9fSShreyas B. Prabhu /*
28177b54e9fSShreyas B. Prabhu * sibling mask for the first cpu. Left shift this by required bits
28277b54e9fSShreyas B. Prabhu * to get sibling mask for the rest of the cpus.
28377b54e9fSShreyas B. Prabhu */
28477b54e9fSShreyas B. Prabhu int sibling_mask_first_cpu = (1 << threads_per_subcore) - 1;
28577b54e9fSShreyas B. Prabhu
28677b54e9fSShreyas B. Prabhu for_each_possible_cpu(cpu) {
28777b54e9fSShreyas B. Prabhu int tid = cpu_thread_in_core(cpu);
28877b54e9fSShreyas B. Prabhu int offset = (tid / threads_per_subcore) * threads_per_subcore;
28977b54e9fSShreyas B. Prabhu int mask = sibling_mask_first_cpu << offset;
29077b54e9fSShreyas B. Prabhu
291d2e60075SNicholas Piggin paca_ptrs[cpu]->subcore_sibling_mask = mask;
29277b54e9fSShreyas B. Prabhu
29377b54e9fSShreyas B. Prabhu }
29477b54e9fSShreyas B. Prabhu }
29577b54e9fSShreyas B. Prabhu
cpu_update_split_mode(void * data)296e2186023SMichael Ellerman static int cpu_update_split_mode(void *data)
297e2186023SMichael Ellerman {
298e2186023SMichael Ellerman int cpu, new_mode = *(int *)data;
299e2186023SMichael Ellerman
300e2186023SMichael Ellerman if (this_cpu_ptr(&split_state)->master) {
301e2186023SMichael Ellerman new_split_mode = new_mode;
302e2186023SMichael Ellerman smp_wmb();
303e2186023SMichael Ellerman
304e2186023SMichael Ellerman cpumask_andnot(cpu_offline_mask, cpu_present_mask,
305e2186023SMichael Ellerman cpu_online_mask);
306e2186023SMichael Ellerman
307e2186023SMichael Ellerman /* This should work even though the cpu is offline */
308e2186023SMichael Ellerman for_each_cpu(cpu, cpu_offline_mask)
309e2186023SMichael Ellerman smp_send_reschedule(cpu);
310e2186023SMichael Ellerman }
311e2186023SMichael Ellerman
312e2186023SMichael Ellerman cpu_do_split(new_mode);
313e2186023SMichael Ellerman
314e2186023SMichael Ellerman if (this_cpu_ptr(&split_state)->master) {
315e2186023SMichael Ellerman /* Wait for all cpus to finish before we touch subcores_per_core */
316e2186023SMichael Ellerman for_each_present_cpu(cpu) {
317e2186023SMichael Ellerman if (cpu >= setup_max_cpus)
318e2186023SMichael Ellerman break;
319e2186023SMichael Ellerman
320e2186023SMichael Ellerman while(per_cpu(split_state, cpu).step < SYNC_STEP_FINISHED)
321e2186023SMichael Ellerman barrier();
322e2186023SMichael Ellerman }
323e2186023SMichael Ellerman
324e2186023SMichael Ellerman new_split_mode = 0;
325e2186023SMichael Ellerman
326e2186023SMichael Ellerman /* Make the new mode public */
327e2186023SMichael Ellerman subcores_per_core = new_mode;
328e2186023SMichael Ellerman threads_per_subcore = threads_per_core / subcores_per_core;
32977b54e9fSShreyas B. Prabhu update_subcore_sibling_mask();
330e2186023SMichael Ellerman
331e2186023SMichael Ellerman /* Make sure the new mode is written before we exit */
332e2186023SMichael Ellerman mb();
333e2186023SMichael Ellerman }
334e2186023SMichael Ellerman
335e2186023SMichael Ellerman return 0;
336e2186023SMichael Ellerman }
337e2186023SMichael Ellerman
set_subcores_per_core(int new_mode)338e2186023SMichael Ellerman static int set_subcores_per_core(int new_mode)
339e2186023SMichael Ellerman {
340e2186023SMichael Ellerman struct split_state *state;
341e2186023SMichael Ellerman int cpu;
342e2186023SMichael Ellerman
343e2186023SMichael Ellerman if (kvm_hv_mode_active()) {
344e2186023SMichael Ellerman pr_err("Unable to change split core mode while KVM active.\n");
345e2186023SMichael Ellerman return -EBUSY;
346e2186023SMichael Ellerman }
347e2186023SMichael Ellerman
348e2186023SMichael Ellerman /*
349e2186023SMichael Ellerman * We are only called at boot, or from the sysfs write. If that ever
350e2186023SMichael Ellerman * changes we'll need a lock here.
351e2186023SMichael Ellerman */
352e2186023SMichael Ellerman BUG_ON(new_mode < 1 || new_mode > 4 || new_mode == 3);
353e2186023SMichael Ellerman
354e2186023SMichael Ellerman for_each_present_cpu(cpu) {
355e2186023SMichael Ellerman state = &per_cpu(split_state, cpu);
356e2186023SMichael Ellerman state->step = SYNC_STEP_INITIAL;
357e2186023SMichael Ellerman state->master = 0;
358e2186023SMichael Ellerman }
359e2186023SMichael Ellerman
360f9a69931SSebastian Andrzej Siewior cpus_read_lock();
361e2186023SMichael Ellerman
362e2186023SMichael Ellerman /* This cpu will update the globals before exiting stop machine */
363e2186023SMichael Ellerman this_cpu_ptr(&split_state)->master = 1;
364e2186023SMichael Ellerman
365e2186023SMichael Ellerman /* Ensure state is consistent before we call the other cpus */
366e2186023SMichael Ellerman mb();
367e2186023SMichael Ellerman
368f9a69931SSebastian Andrzej Siewior stop_machine_cpuslocked(cpu_update_split_mode, &new_mode,
369f9a69931SSebastian Andrzej Siewior cpu_online_mask);
370e2186023SMichael Ellerman
371f9a69931SSebastian Andrzej Siewior cpus_read_unlock();
372e2186023SMichael Ellerman
373e2186023SMichael Ellerman return 0;
374e2186023SMichael Ellerman }
375e2186023SMichael Ellerman
store_subcores_per_core(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)376e2186023SMichael Ellerman static ssize_t __used store_subcores_per_core(struct device *dev,
377e2186023SMichael Ellerman struct device_attribute *attr, const char *buf,
378e2186023SMichael Ellerman size_t count)
379e2186023SMichael Ellerman {
380e2186023SMichael Ellerman unsigned long val;
381e2186023SMichael Ellerman int rc;
382e2186023SMichael Ellerman
383e2186023SMichael Ellerman /* We are serialised by the attribute lock */
384e2186023SMichael Ellerman
385e2186023SMichael Ellerman rc = sscanf(buf, "%lx", &val);
386e2186023SMichael Ellerman if (rc != 1)
387e2186023SMichael Ellerman return -EINVAL;
388e2186023SMichael Ellerman
389e2186023SMichael Ellerman switch (val) {
390e2186023SMichael Ellerman case 1:
391e2186023SMichael Ellerman case 2:
392e2186023SMichael Ellerman case 4:
393e2186023SMichael Ellerman if (subcores_per_core == val)
394e2186023SMichael Ellerman /* Nothing to do */
395e2186023SMichael Ellerman goto out;
396e2186023SMichael Ellerman break;
397e2186023SMichael Ellerman default:
398e2186023SMichael Ellerman return -EINVAL;
399e2186023SMichael Ellerman }
400e2186023SMichael Ellerman
401e2186023SMichael Ellerman rc = set_subcores_per_core(val);
402e2186023SMichael Ellerman if (rc)
403e2186023SMichael Ellerman return rc;
404e2186023SMichael Ellerman
405e2186023SMichael Ellerman out:
406e2186023SMichael Ellerman return count;
407e2186023SMichael Ellerman }
408e2186023SMichael Ellerman
show_subcores_per_core(struct device * dev,struct device_attribute * attr,char * buf)409e2186023SMichael Ellerman static ssize_t show_subcores_per_core(struct device *dev,
410e2186023SMichael Ellerman struct device_attribute *attr, char *buf)
411e2186023SMichael Ellerman {
412e2186023SMichael Ellerman return sprintf(buf, "%x\n", subcores_per_core);
413e2186023SMichael Ellerman }
414e2186023SMichael Ellerman
415e2186023SMichael Ellerman static DEVICE_ATTR(subcores_per_core, 0644,
416e2186023SMichael Ellerman show_subcores_per_core, store_subcores_per_core);
417e2186023SMichael Ellerman
subcore_init(void)418e2186023SMichael Ellerman static int subcore_init(void)
419e2186023SMichael Ellerman {
4200e5e7f5eSMichael Ellerman struct device *dev_root;
4210e5e7f5eSMichael Ellerman unsigned pvr_ver;
4220e5e7f5eSMichael Ellerman int rc = 0;
4230e5e7f5eSMichael Ellerman
4240e5e7f5eSMichael Ellerman pvr_ver = PVR_VER(mfspr(SPRN_PVR));
4250e5e7f5eSMichael Ellerman
4260e5e7f5eSMichael Ellerman if (pvr_ver != PVR_POWER8 &&
427e2186023SMichael Ellerman pvr_ver != PVR_POWER8E &&
428e2186023SMichael Ellerman pvr_ver != PVR_POWER8NVL)
429e2186023SMichael Ellerman return 0;
430e2186023SMichael Ellerman
431e2186023SMichael Ellerman /*
432e2186023SMichael Ellerman * We need all threads in a core to be present to split/unsplit so
433e2186023SMichael Ellerman * continue only if max_cpus are aligned to threads_per_core.
434e2186023SMichael Ellerman */
435e2186023SMichael Ellerman if (setup_max_cpus % threads_per_core)
436e2186023SMichael Ellerman return 0;
437e2186023SMichael Ellerman
438e2186023SMichael Ellerman BUG_ON(!alloc_cpumask_var(&cpu_offline_mask, GFP_KERNEL));
439e2186023SMichael Ellerman
440e2186023SMichael Ellerman set_subcores_per_core(1);
441e2186023SMichael Ellerman
442e2186023SMichael Ellerman dev_root = bus_get_dev_root(&cpu_subsys);
443e2186023SMichael Ellerman if (dev_root) {
444 rc = device_create_file(dev_root, &dev_attr_subcores_per_core);
445 put_device(dev_root);
446 }
447 return rc;
448 }
449 machine_device_initcall(powernv, subcore_init);
450