Lines Matching +full:sync +full:- +full:update +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0
65 * struct crystalcove_gpio - Crystal Cove GPIO controller
66 * @buslock: for bus lock/sync and unlock.
69 * @update: pending IRQ setting update, to be written to the chip upon unlock.
71 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
77 int update; member
95 return -ENOTSUPP; in to_reg()
117 int mask = BIT(gpio % 8); in crystalcove_update_irq_mask() local
119 if (cg->set_irq_mask) in crystalcove_update_irq_mask()
120 regmap_update_bits(cg->regmap, mirqs0, mask, mask); in crystalcove_update_irq_mask()
122 regmap_update_bits(cg->regmap, mirqs0, mask, 0); in crystalcove_update_irq_mask()
129 regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value); in crystalcove_update_irq_ctrl()
140 return regmap_write(cg->regmap, reg, CTLO_INPUT_SET); in crystalcove_gpio_dir_in()
151 return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value); in crystalcove_gpio_dir_out()
163 ret = regmap_read(cg->regmap, reg, &val); in crystalcove_gpio_get()
179 regmap_update_bits(cg->regmap, reg, 1, 1); in crystalcove_gpio_set()
181 regmap_update_bits(cg->regmap, reg, 1, 0); in crystalcove_gpio_set()
194 cg->intcnt_value = CTLI_INTCNT_DIS; in crystalcove_irq_type()
197 cg->intcnt_value = CTLI_INTCNT_BE; in crystalcove_irq_type()
200 cg->intcnt_value = CTLI_INTCNT_PE; in crystalcove_irq_type()
203 cg->intcnt_value = CTLI_INTCNT_NE; in crystalcove_irq_type()
206 return -EINVAL; in crystalcove_irq_type()
209 cg->update |= UPDATE_IRQ_TYPE; in crystalcove_irq_type()
218 mutex_lock(&cg->buslock); in crystalcove_bus_lock()
226 if (cg->update & UPDATE_IRQ_TYPE) in crystalcove_bus_sync_unlock()
228 if (cg->update & UPDATE_IRQ_MASK) in crystalcove_bus_sync_unlock()
230 cg->update = 0; in crystalcove_bus_sync_unlock()
232 mutex_unlock(&cg->buslock); in crystalcove_bus_sync_unlock()
246 cg->set_irq_mask = false; in crystalcove_irq_unmask()
247 cg->update |= UPDATE_IRQ_MASK; in crystalcove_irq_unmask()
259 cg->set_irq_mask = true; in crystalcove_irq_mask()
260 cg->update |= UPDATE_IRQ_MASK; in crystalcove_irq_mask()
284 if (regmap_read(cg->regmap, GPIO0IRQ, &p0) || in crystalcove_gpio_irq_handler()
285 regmap_read(cg->regmap, GPIO1IRQ, &p1)) in crystalcove_gpio_irq_handler()
288 regmap_write(cg->regmap, GPIO0IRQ, p0); in crystalcove_gpio_irq_handler()
289 regmap_write(cg->regmap, GPIO1IRQ, p1); in crystalcove_gpio_irq_handler()
294 virq = irq_find_mapping(cg->chip.irq.domain, gpio); in crystalcove_gpio_irq_handler()
308 regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); in crystalcove_gpio_dbg_show()
309 regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli); in crystalcove_gpio_dbg_show()
310 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0, in crystalcove_gpio_dbg_show()
312 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX, in crystalcove_gpio_dbg_show()
314 regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ, in crystalcove_gpio_dbg_show()
318 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n", in crystalcove_gpio_dbg_show()
324 mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask", in crystalcove_gpio_dbg_show()
325 mirqsx & BIT(offset) ? "sx mask " : "sx unmask", in crystalcove_gpio_dbg_show()
335 struct device *dev = pdev->dev.parent; in crystalcove_gpio_probe()
342 cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL); in crystalcove_gpio_probe()
344 return -ENOMEM; in crystalcove_gpio_probe()
346 mutex_init(&cg->buslock); in crystalcove_gpio_probe()
347 cg->chip.label = KBUILD_MODNAME; in crystalcove_gpio_probe()
348 cg->chip.direction_input = crystalcove_gpio_dir_in; in crystalcove_gpio_probe()
349 cg->chip.direction_output = crystalcove_gpio_dir_out; in crystalcove_gpio_probe()
350 cg->chip.get = crystalcove_gpio_get; in crystalcove_gpio_probe()
351 cg->chip.set = crystalcove_gpio_set; in crystalcove_gpio_probe()
352 cg->chip.base = -1; in crystalcove_gpio_probe()
353 cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM; in crystalcove_gpio_probe()
354 cg->chip.can_sleep = true; in crystalcove_gpio_probe()
355 cg->chip.parent = dev; in crystalcove_gpio_probe()
356 cg->chip.dbg_show = crystalcove_gpio_dbg_show; in crystalcove_gpio_probe()
357 cg->regmap = pmic->regmap; in crystalcove_gpio_probe()
359 girq = &cg->chip.irq; in crystalcove_gpio_probe()
362 girq->parent_handler = NULL; in crystalcove_gpio_probe()
363 girq->num_parents = 0; in crystalcove_gpio_probe()
364 girq->parents = NULL; in crystalcove_gpio_probe()
365 girq->default_type = IRQ_TYPE_NONE; in crystalcove_gpio_probe()
366 girq->handler = handle_simple_irq; in crystalcove_gpio_probe()
367 girq->threaded = true; in crystalcove_gpio_probe()
369 retval = devm_request_threaded_irq(&pdev->dev, irq, NULL, in crystalcove_gpio_probe()
373 dev_warn(&pdev->dev, "request irq failed: %d\n", retval); in crystalcove_gpio_probe()
377 retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg); in crystalcove_gpio_probe()
382 irq_domain_update_bus_token(cg->chip.irq.domain, DOMAIN_BUS_WIRED); in crystalcove_gpio_probe()