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/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,sm8550-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
21 See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
26 - qcom,sm8550-aggre1-noc
27 - qcom,sm8550-aggre2-noc
28 - qcom,sm8550-clk-virt
29 - qcom,sm8550-cnoc-main
30 - qcom,sm8550-config-noc
31 - qcom,sm8550-gem-noc
32 - qcom,sm8550-lpass-ag-noc
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sm8550-pas.yaml4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml#
7 title: Qualcomm SM8550 Peripheral Authentication Service
13 Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware
19 - qcom,sm8550-adsp-pas
20 - qcom,sm8550-cdsp-pas
21 - qcom,sm8550-mpss-pas
64 - qcom,sm8550-adsp-pas
65 - qcom,sm8550-cdsp-pas
87 - qcom,sm8550-adsp-pas
103 - qcom,sm8550-mpss-pas
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/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm8550-mdss.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
7 title: Qualcomm SM8550 Display MDSS
13 SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
20 const: qcom,sm8550-mdss
43 const: qcom,sm8550-dpu
50 - const: qcom,sm8550-dp
58 - const: qcom,sm8550-dsi-ctrl
65 const: qcom,sm8550-dsi-phy-4nm
74 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
75 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
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H A Dqcom,sm8550-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
7 title: Qualcomm SM8550 Display DPU
16 const: qcom,sm8550-dpu
57 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
58 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
63 compatible = "qcom,sm8550-dpu";
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8550-tcsr.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
7 title: Qualcomm TCSR Clock Controller on SM8550
14 power domains on SM8550
16 See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
21 - const: qcom,sm8550-tcsr
48 compatible = "qcom,sm8550-tcsr", "syscon";
H A Dqcom,sm8550-gcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8550
14 domains on SM8550
16 See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
20 const: qcom,sm8550-gcc
47 compatible = "qcom,sm8550-gcc";
H A Dqcom,sm8550-dispcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8550
15 domains on SM8550.
17 See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
22 - qcom,sm8550-dispcc
77 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
81 compatible = "qcom,sm8550-dispcc";
H A Dqcom,sm8450-gpucc.yaml18 include/dt-bindings/clock/qcom,sm8550-gpucc.h
25 - qcom,sm8550-gpucc
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm8550-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8550 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC.
19 const: qcom,sm8550-lpass-lpi-pinctrl
49 - $ref: "#/$defs/qcom-sm8550-lpass-state"
52 $ref: "#/$defs/qcom-sm8550-lpass-state"
56 qcom-sm8550-lpass-state:
132 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
H A Dqcom,sm8550-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SM8550 TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC.
20 const: qcom,sm8550-tlmm
44 - $ref: "#/$defs/qcom-sm8550-tlmm-state"
47 $ref: "#/$defs/qcom-sm8550-tlmm-state"
51 qcom-sm8550-tlmm-state:
126 compatible = "qcom,sm8550-tlmm";
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,snps-eusb2-phy.yaml17 const: qcom,sm8550-snps-eusb2-phy
63 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
65 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
68 compatible = "qcom,sm8550-snps-eusb2-phy";
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml37 - qcom,sm8550-qmp-gen3x2-pcie-phy
38 - qcom,sm8550-qmp-gen4x2-pcie-phy
148 - qcom,sm8550-qmp-gen3x2-pcie-phy
149 - qcom,sm8550-qmp-gen4x2-pcie-phy
191 - qcom,sm8550-qmp-gen4x2-pcie-phy
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dqcom,inline-crypto-engine.yaml17 - qcom,sm8550-inline-crypto-engine
35 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
38 compatible = "qcom,sm8550-inline-crypto-engine",
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm8550-mtp.dts9 #include "sm8550.dtsi"
19 model = "Qualcomm Technologies, Inc. SM8550 MTP";
20 compatible = "qcom,sm8550-mtp", "qcom,sm8550";
58 compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
100 compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
101 model = "SM8550-MTP";
664 firmware-name = "qcom/sm8550/adsp.mbn",
665 "qcom/sm8550/adsp_dtb.mbn";
670 firmware-name = "qcom/sm8550/cdsp.mbn",
671 "qcom/sm8550/cdsp_dtb.mbn";
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H A Dsm8550-qrd.dts10 #include "sm8550.dtsi"
20 model = "Qualcomm Technologies, Inc. SM8550 QRD";
21 compatible = "qcom,sm8550-qrd", "qcom,sm8550";
75 compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
117 compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
118 model = "SM8550-QRD";
370 /* ldo2 supplies SM8550 VDD_LPI_MX */
769 firmware-name = "qcom/sm8550/adsp.mbn",
770 "qcom/sm8550/adsp_dtb.mbn";
775 firmware-name = "qcom/sm8550/cdsp.mbn",
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H A Dsm8550.dtsi8 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
10 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
11 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
15 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
334 compatible = "qcom,scm-sm8550", "qcom,scm";
340 compatible = "qcom,sm8550-clk-virt";
346 compatible = "qcom,sm8550-mc-virt";
769 compatible = "qcom,sm8550-gcc";
785 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
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/openbmc/linux/drivers/clk/qcom/
H A Dtcsrcc-sm8550.c14 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
170 { .compatible = "qcom,sm8550-tcsr", .data = &tcsr_cc_sm8550_desc },
189 .name = "tcsr_cc-sm8550",
206 MODULE_DESCRIPTION("QTI TCSRCC SM8550 Driver");
H A DMakefile111 obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o
121 obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
130 obj-$(CONFIG_SM_GPUCC_8550) += gpucc-sm8550.o
131 obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
136 obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o
H A DKconfig829 tristate "SM8550 Display Clock Controller"
834 SM8550 devices.
918 tristate "SM8550 Global Clock Controller"
922 Support for the global clock controller on SM8550 devices.
999 tristate "SM8550 Graphics Clock Controller"
1003 Support for the graphics clock controller on SM8550 devices.
1008 tristate "SM8550 TCSR Clock Controller"
1012 Support for the TCSR clock controller on SM8550 devices.
1046 tristate "SM8550 Video Clock Controller"
1052 SM8550 devices.
/openbmc/linux/drivers/interconnect/qcom/
H A DMakefile31 qnoc-sm8550-objs := sm8550.o
59 obj-$(CONFIG_INTERCONNECT_QCOM_SM8550) += qnoc-sm8550.o
H A Dsm8550.c16 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
21 #include "sm8550.h"
2188 { .compatible = "qcom,sm8550-aggre1-noc",
2190 { .compatible = "qcom,sm8550-aggre2-noc",
2192 { .compatible = "qcom,sm8550-clk-virt",
2194 { .compatible = "qcom,sm8550-config-noc",
2196 { .compatible = "qcom,sm8550-cnoc-main",
2198 { .compatible = "qcom,sm8550-gem-noc",
2200 { .compatible = "qcom,sm8550-lpass-ag-noc",
2202 { .compatible = "qcom,sm8550-lpass-lpiaon-noc",
[all …]
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dqcom,scm.yaml63 - qcom,scm-sm8550
181 - qcom,scm-sm8550
194 - qcom,scm-sm8550
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-rx-macro.yaml18 - qcom,sm8550-lpass-rx-macro
100 - qcom,sm8550-lpass-rx-macro
H A Dqcom,lpass-va-macro.yaml18 - qcom,sm8550-lpass-va-macro
119 - qcom,sm8550-lpass-va-macro
H A Dqcom,lpass-wsa-macro.yaml18 - qcom,sm8550-lpass-wsa-macro
98 - qcom,sm8550-lpass-wsa-macro

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