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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48 |
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| #
377107bc |
| 20-Aug-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
dt-bindings: phy: qcom,qmp-pcie: describe SM8150 PCIe PHYs
Descrbie two PCIe PHYs found on the Qualcomm SM8150 platform, single
lane and two lanes Gen3 PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry
dt-bindings: phy: qcom,qmp-pcie: describe SM8150 PCIe PHYs
Descrbie two PCIe PHYs found on the Qualcomm SM8150 platform, single
lane and two lanes Gen3 PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
show more ...
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| #
505fb254 |
| 20-Aug-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml
Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml)
to qcom,sc8280xp-qmp-pcie-phy.yaml. This remo
dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml
Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml)
to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare
the child PHY node or split resource regions.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
show more ...
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Revision tags: v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39 |
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| #
fd2d4e4c |
| 14-Jul-2023 |
Mrinmay Sarkar <quic_msarkar@quicinc.com> |
dt-bindings: phy: qcom,qmp: Add sa8775p QMP PCIe PHY
Add devicetree YAML binding for Qualcomm QMP PCIe PHY
for SA8775p platform.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Link: https
dt-bindings: phy: qcom,qmp: Add sa8775p QMP PCIe PHY
Add devicetree YAML binding for Qualcomm QMP PCIe PHY
for SA8775p platform.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Link: https://lore.kernel.org/r/1689311319-22054-3-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
show more ...
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Revision tags: v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20 |
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| #
0d678713 |
| 17-Mar-2023 |
Rohit Agarwal <quic_rohiagar@quicinc.com> |
dt-bindings: phy: qcom,qmp: Add SDX65 QMP PHY
Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found
in SDX65.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Acked-by: Kr
dt-bindings: phy: qcom,qmp: Add SDX65 QMP PHY
Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found
in SDX65.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1679035114-19879-2-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
show more ...
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Revision tags: v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11 |
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| #
496d068e |
| 08-Feb-2023 |
Abel Vesa <abel.vesa@linaro.org> |
dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550
Document the QMP PCIe PHY compatible for SM8550.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.
dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550
Document the QMP PCIe PHY compatible for SM8550.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-2-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
show more ...
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Revision tags: v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80 |
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| #
43a6a29b |
| 18-Nov-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
dt-bindings: phy: qcom,qmp-pcie: add sm8350 bindings
Add bindings for the PCIe QMP PHYs found on SM8350.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.or
dt-bindings: phy: qcom,qmp-pcie: add sm8350 bindings
Add bindings for the PCIe QMP PHYs found on SM8350.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221118233242.2904088-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Revision tags: v6.0.9, v5.15.79, v6.0.8, v5.15.78 |
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| #
30638230 |
| 05-Nov-2022 |
Johan Hovold <johan+linaro@kernel.org> |
dt-bindings: phy: qcom,qmp-pcie: add sc8280xp bindings
Add bindings for the PCIe QMP PHYs found on SC8280XP.
The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in
4-lane mode or as se
dt-bindings: phy: qcom,qmp-pcie: add sc8280xp bindings
Add bindings for the PCIe QMP PHYs found on SC8280XP.
The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in
4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as
PCIe2A and PCIe2B).
The configuration for a specific system can be read from a TCSR register.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-12-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
show more ...
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